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[Qemu-devel] [PATCH 076/111] m68k: register source operand is always in
From: |
Bryce Lanham |
Subject: |
[Qemu-devel] [PATCH 076/111] m68k: register source operand is always in extended size |
Date: |
Wed, 17 Aug 2011 15:47:21 -0500 |
From: Laurent Vivier <address@hidden>
Allow Xvnc4 to run.
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/translate.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 61ec317..4f73bf8 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3637,11 +3637,12 @@ DISAS_INSN(fpu)
gen_op_fmovem(s, insn, ext);
return;
}
- opsize = ext_opsize(ext, 10);
if (ext & (1 << 14)) {
+ opsize = ext_opsize(ext, 10);
gen_op_load_ea_FP0(s, insn, opsize);
} else {
/* Source register. */
+ opsize = OS_EXTENDED;
gen_op_load_fpr_FP0(REG(ext, 10));
}
round = 1;
--
1.7.2.3
- [Qemu-devel] [PATCH 030/111] m68k: add FScc instruction, (continued)
- [Qemu-devel] [PATCH 030/111] m68k: add FScc instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 031/111] m68k: add single data type to gen_ea, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 039/111] m68k: add abcd instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 035/111] m68k: improve CC_OP_LOGIC, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 037/111] Correct invalid use of "const void *" with "const uint8_t *", Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 041/111] mm68k: add nbcd instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 050/111] m68k: lsl/lsr, clear C flag if shift count is 0, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 043/111] m68k: on 0 bit shift, don't update X flag, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 075/111] m68k: better fpu traces, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 062/111] m68k: FPU rework (draft), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 076/111] m68k: register source operand is always in extended size,
Bryce Lanham <=
- [Qemu-devel] [PATCH 074/111] m68k: add ftwotox instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 060/111] m68k: remove dead code, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 045/111] m68k: improve subx, negx instructions Add (byte, word) opsize Add memory access (subx), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 070/111] m68k: initialize FRegs, define pickNaN(), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 042/111] m68k: set X flag according size of operand Set X flag correctly for addsub, arith_im, addsubq., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 085/111] m68k: add fatan instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 073/111] m68k: add cmpm instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 055/111] m68k: Correct bfclr in register case., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 054/111] m68k: Added ULL to 64 bit integer in helper.c, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 040/111] m68k: add sbcd instruction, Bryce Lanham, 2011/08/17