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[Qemu-devel] [PATCH 05/16] S3C Clock controller peripheral
From: |
Vincent Sanders |
Subject: |
[Qemu-devel] [PATCH 05/16] S3C Clock controller peripheral |
Date: |
Thu, 23 Apr 2009 18:58:23 +0100 |
User-agent: |
Mutt/1.5.17+20080114 (2008-01-14) |
S3C Clock control support.
Signed-off-by: Vincent Sanders <address@hidden>
---
s3c24xx_clkcon.c | 100 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 100 insertions(+)
diff -urN qemusvnclean/hw/s3c24xx_clkcon.c qemusvnpatches/hw/s3c24xx_clkcon.c
--- qemusvnclean/hw/s3c24xx_clkcon.c 1970-01-01 01:00:00.000000000 +0100
+++ qemusvnpatches/hw/s3c24xx_clkcon.c 2009-04-23 16:00:56.000000000 +0100
@@ -0,0 +1,100 @@
+/* hw/s3c24xx_clkcon.c
+ *
+ * Samsung S3C24XX Clock control emulation
+ *
+ * Copyright 2006, 2007, 2008 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2
+ */
+
+#include "hw.h"
+
+#include "s3c24xx.h"
+
+/* Lock time RW */
+#define S3C_REG_LOCKTIME 0
+
+/* MPLL Control RW */
+#define S3C_REG_MPLLCON 1
+
+/* UPLL Control RW */
+#define S3C_REG_UPLLCON 2
+
+/* Clock Generator Control RW */
+#define S3C_REG_CLKCON 3
+
+/* CLKCON IDLE */
+#define S3C_REG_CLKCON_IDLE (1<<2)
+
+/* Slow Clock Control RW */
+#define S3C_REG_CLKSLOW 4
+
+/* Clock divider control RW */
+#define S3C_REG_CLKDIVN 5
+
+static void
+s3c24xx_clkcon_write_f(void *opaque, target_phys_addr_t addr_, uint32_t value)
+{
+ S3CState *soc = (S3CState *)opaque;
+ int addr = (addr_ & 0x1F) >> 2;
+ int idle_rising_edge = 0;
+
+ if (addr < 0 || addr > 5)
+ addr = 5;
+
+ if (addr == S3C_REG_CLKCON) {
+ if( !(soc->clkcon_reg[addr] & S3C_REG_CLKCON_IDLE) &&
+ (value & S3C_REG_CLKCON_IDLE) ) idle_rising_edge = 1;
+ }
+ soc->clkcon_reg[addr] = value;
+ if (idle_rising_edge) {
+ cpu_interrupt(soc->cpu_env, CPU_INTERRUPT_HALT);
+ }
+}
+
+static uint32_t
+s3c24xx_clkcon_read_f(void *opaque, target_phys_addr_t addr_)
+{
+ S3CState *soc = (S3CState *)opaque;
+ int addr = (addr_ & 0x1F) >> 2;
+
+ if (addr < 0 || addr > 5)
+ addr = 5;
+
+ return soc->clkcon_reg[addr];
+}
+
+static CPUReadMemoryFunc *s3c24xx_clkcon_read[] = {
+ &s3c24xx_clkcon_read_f,
+ &s3c24xx_clkcon_read_f,
+ &s3c24xx_clkcon_read_f,
+};
+
+static CPUWriteMemoryFunc *s3c24xx_clkcon_write[] = {
+ &s3c24xx_clkcon_write_f,
+ &s3c24xx_clkcon_write_f,
+ &s3c24xx_clkcon_write_f,
+};
+
+
+void
+s3c24xx_clkcon_init(S3CState *soc, target_phys_addr_t base_addr)
+{
+ int tag;
+
+ tag = cpu_register_io_memory(0, s3c24xx_clkcon_read, s3c24xx_clkcon_write,
soc);
+ cpu_register_physical_memory(base_addr, 6 * 4, tag);
+
+ /* initialise register values to power on defaults */
+ soc->clkcon_reg[S3C_REG_LOCKTIME] = 0x00FFFFFF;
+ soc->clkcon_reg[S3C_REG_MPLLCON] = 0x0005C080;
+ soc->clkcon_reg[S3C_REG_UPLLCON] = 0x00028080;
+ soc->clkcon_reg[S3C_REG_CLKCON] = 0x0007FFF0;
+ soc->clkcon_reg[S3C_REG_CLKSLOW] = 0x00000004;
+ soc->clkcon_reg[S3C_REG_CLKDIVN] = 0x00000000;
+
+ /* Currently it is assumed the t1 clock will be fed by a 12MHz source */
+ soc->tclk1 = 12000000;
+
+}
--
Regards Vincent
http://www.kyllikki.org/
- [Qemu-devel] [PATCH 0/16] ARM Add S3C SOC core, drivers and boards, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 1/16] ARM Add ARM 920T identifiers, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 2/16] Add s3c SOC header, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 3/16] S3C SDRAM memory controller Peripheral, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 4/16] S3C irq controller, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 05/16] S3C Clock controller peripheral,
Vincent Sanders <=
- [Qemu-devel] [PATCH 7/16] S3C serial peripheral, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 6/16] S3C Timers, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 8/16] S3C Real Time Clock, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 9/16] S3C General Purpose IO, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 10/16] S3C I2C peripheral, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 11/16] S3C LCD display, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 12/16] S3C NAND controller, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 13/16] S3C2410 SOC implementation, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 14/16] S3C2440 SOC impementation, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 15/16] Add S3C SOC files to Makefile, Vincent Sanders, 2009/04/23