[Qemu-devel] [PATCH 2/16] Add s3c SOC header

[Vincent Sanders]

S3C SOC integrated peripheral devices structure

Signed-off-by: Vincent Sanders <address@hidden>
---
 s3c24xx.h |   73 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)


diff -urN qemusvnclean/hw/s3c24xx.h qemusvnpatches/hw/s3c24xx.h
--- qemusvnclean/hw/s3c24xx.h   1970-01-01 01:00:00.000000000 +0100
+++ qemusvnpatches/hw/s3c24xx.h 2009-04-23 15:53:57.000000000 +0100
@@ -0,0 +1,73 @@
+/* hw/s3c24xx.h
+ *
+ * Samsung s3c24xx cpu state and functions.
+ *
+ * Copyright 2006, 2007, 2008 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2.
+ */
+
+#ifndef S3C24XX_H
+#define S3C24XX_H 1
+
+/* This structure type encapsulates the state of a S3C24XX SoC. */
+typedef struct S3CState_s {
+    CPUState *cpu_env;
+    qemu_irq *irqs;
+    qemu_irq *eirqs;
+
+    /* Memory controller */
+    uint32_t memc_reg[13];
+
+    /* Interrupt controller */
+    uint32_t irq_main_level, irq_subsrc_level;
+    uint32_t irq_reg[8];
+
+    /* Clock controller */
+    uint32_t clkcon_reg[6];
+
+    uint32_t tclk0; /* first timer clock source frequency */
+    uint32_t tclk1; /* second timer clock source frequency */
+
+    /* GPIO block */
+    uint32_t gpio_reg[47];
+
+    /* Realtime clock */
+    uint8_t rtc_reg[19];
+
+    /* i2c */
+    struct s3c24xx_i2c_state_s *iic;
+    
+    /* Timers, (Specifically timer4) */
+    uint32_t timers_reg[17];
+    QEMUTimer *timer4;
+    uint32_t timer4_reload_value;
+    int64_t timer4_last_ticked;
+
+    /* LCD controller */
+    struct s3c24xx_lcd_state_s *lcd;
+
+    /* NAND controller, and chip attached */
+    uint32_t nand_reg[5];
+    struct nand_flash_s *nand_chip;
+} S3CState;
+
+/* Internal functions for s3c24xx implementation */
+void s3c24xx_memc_init(S3CState *soc, target_phys_addr_t base_addr);
+qemu_irq *s3c24xx_irq_init(S3CState *soc, target_phys_addr_t base_addr);
+void s3c24xx_clkcon_init(S3CState *soc, target_phys_addr_t base_addr);
+void s3c24xx_timers_init(S3CState *soc, target_phys_addr_t base_addr);
+void s3c24xx_serial_init(S3CState *soc, int port, target_phys_addr_t 
base_addr);
+void s3c24xx_rtc_init(S3CState *soc, target_phys_addr_t base_addr);
+void s3c24xx_gpio_init(S3CState *soc, target_phys_addr_t base_addr,uint32_t 
cpu_id );
+void s3c24xx_iic_init(S3CState *soc, target_phys_addr_t base_addr);
+struct s3c24xx_lcd_state_s *s3c24xx_lcd_init(target_phys_addr_t base, qemu_irq 
irq);
+void s3c24xx_nand_init(S3CState *soc, target_phys_addr_t base_addr);
+
+/* attach a NAND device to the s3c24xx controller */
+void s3c24xx_nand_attach(S3CState *soc, struct nand_flash_s *nand_chip);
+
+i2c_bus *s3c24xx_i2c_bus(struct s3c24xx_i2c_state_s *s);
+
+#endif /* S3C24XX_H */

-- 
Regards Vincent
http://www.kyllikki.org/