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[Qemu-devel] Re: ix64 target support

From: Andi Kleen
Subject: [Qemu-devel] Re: ix64 target support
Date: Wed, 29 Sep 2004 11:35:14 +0200
User-agent: Gnus/5.110003 (No Gnus v0.3) Emacs/21.2 (gnu/linux)

Kyle Hayes <address@hidden> writes:

> On Tuesday 28 September 2004 14:37, Joe Batt wrote:
>> Actually, I'm just interested in 64bit address space, so any 64 bit chip
>> with a Linux distro would be great.  Would some old 64 bit risc chip
>> (Alhpa or HPPA) be easier?
>> I assume a lot of the interrupt and memory management can be adapted
>> from the x86 qemu code.  The SH2 was pretty simple in this respect and
>> there was only one "mode".  Anyone out there want to help me work though
>> some of this?
> I think you'll find that the x86-64/AMD64 opcodes and behavior are very, 
> very similar to the x86 specifications.  However, a lot of little things 
> differ in system instructions (i.e. not user instructions).  The page 

Actually not that many differences on the kernel side neither.

> translation tables are similar, but different for instance.  There are 

They are the same as IA32/PAE, just four levels and the third level
is a full page, not only four entries like on IA32.
But the entries in the page tables are the same.

> slightly more TLBs (not that this would make a difference to Qemu I 
> think).

Depends on the CPU. The Intel 64bit Xeons don't have that much
more TLBs.

> I believe that a large number of instructions are functionally identical to 
> the older 32-bit versions.  Where differences exist, they tend to be 
> across many instructions.  I.e. when doing 32-bit operations, the top 
> 32-bits of each 64-bit register is treated somewhat consistently (zeroed I 
> think).

Basically yes. And you have the 64bit override prefixes, which
allow to access the extended registers and use 64bit instructions.
It also has the RIP relative addressing mode there.

And there are two new instructions: movabs (to load 64bit constants) 
and swapgs for the kernel.

> It will be the modes and how to handle things like traps (what to push on 
> the stack etc.) that are going to be a bit nasty.  Not that the x86 chips 
> are clean mind you :-)

It's not that different. The main difference is that all the values
in the stack frame are 8 bytes, not 4 bytes. 

There are some other differences in the stack frames, but they 
should be relatively easy to handle.

You'll have to handle compat mode for a full system emulation 
(32bit programs on 64bit kernel), which can be a bit tricky.

Overall it should be relatively straight forward to convert it over.
Someone did the port of Bochs also in a short time.

>> Volume 3 from
>> http://www.amd.com/us-en/Processors/DevelopWithAMD/0,,30_2252_739_7044,0
>>0.html lists all the opcodes and what they do.  I started the SH2
>> emulator by writing tests for each opcode, then the implementation from
>> a document like this.  Is there anything else I need to evaluate before
>> I start implementing opcodes?
> I think I'd start by trying to see the differences between the instruction 
> sets first.  Get a feel for it.  Remember that AMD64 is a 16/32/64-bit 
> instruction set :-/

There is an older document from AMD that just lists the differences
from 32bit to 64bit (not sure if it's still available, they switched
to full manuals some time ago) Intel also has a similar document on
their website that documents the delta from IA32 to x86-64 in
their flavour of AMD64 (which is practically identical to AMD's except
that they call it EM64T)


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