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Re: [Qemu-devel] ix64 target support

From: Kyle Hayes
Subject: Re: [Qemu-devel] ix64 target support
Date: Tue, 28 Sep 2004 20:17:51 -0700
User-agent: KMail/1.5.4

On Tuesday 28 September 2004 14:37, Joe Batt wrote:
> Actually, I'm just interested in 64bit address space, so any 64 bit chip
> with a Linux distro would be great.  Would some old 64 bit risc chip
> (Alhpa or HPPA) be easier?
> I assume a lot of the interrupt and memory management can be adapted
> from the x86 qemu code.  The SH2 was pretty simple in this respect and
> there was only one "mode".  Anyone out there want to help me work though
> some of this?

I think you'll find that the x86-64/AMD64 opcodes and behavior are very, 
very similar to the x86 specifications.  However, a lot of little things 
differ in system instructions (i.e. not user instructions).  The page 
translation tables are similar, but different for instance.  There are 
slightly more TLBs (not that this would make a difference to Qemu I 

I believe that a large number of instructions are functionally identical to 
the older 32-bit versions.  Where differences exist, they tend to be 
across many instructions.  I.e. when doing 32-bit operations, the top 
32-bits of each 64-bit register is treated somewhat consistently (zeroed I 

It will be the modes and how to handle things like traps (what to push on 
the stack etc.) that are going to be a bit nasty.  Not that the x86 chips 
are clean mind you :-)

> Volume 3 from
> http://www.amd.com/us-en/Processors/DevelopWithAMD/0,,30_2252_739_7044,0
>0.html lists all the opcodes and what they do.  I started the SH2
> emulator by writing tests for each opcode, then the implementation from
> a document like this.  Is there anything else I need to evaluate before
> I start implementing opcodes?

I think I'd start by trying to see the differences between the instruction 
sets first.  Get a feel for it.  Remember that AMD64 is a 16/32/64-bit 
instruction set :-/


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