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[PATCH v6 36/42] target/arm: Complete TBI clearing for user-only for SVE
From: |
Richard Henderson |
Subject: |
[PATCH v6 36/42] target/arm: Complete TBI clearing for user-only for SVE |
Date: |
Thu, 12 Mar 2020 12:42:13 -0700 |
There are a number of paths by which the TBI is still intact
for user-only in the SVE helpers.
Because we currently always set TBI for user-only, we do not
need to pass down the actual TBI setting from above, and we
can remove the top byte in the inner-most primitives, so that
none are forgotten. Moreover, this keeps the "dirty" pointer
around at the higher levels, where we need it for any MTE checking.
Since the normal case, especially for user-only, goes through
RAM, this clearing merely adds two insns per page lookup, which
will be completely in the noise.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/sve_helper.c | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 566a619300..f0afbd0faf 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -3985,7 +3985,7 @@ typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd,
intptr_t reg_off,
*
* For *_tlb, this uses the cpu_*_data_ra helpers. There are not
* endian-specific versions of these, so we must handle endianness
- * locally.
+ * locally. See sve_probe_page about TBI.
*
* For *_host, this is a trivial application of the <qemu/bswap.h>
* endian-specific access followed by a store into the vector register.
@@ -4009,7 +4009,7 @@ static void sve_##NAME##_host(void *vd, intptr_t reg_off,
void *host) \
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
target_ulong addr, uintptr_t ra) \
{ \
- TYPEM val = BSWAP(TLB(env, addr, ra)); \
+ TYPEM val = BSWAP(TLB(env, useronly_clean_ptr(addr), ra)); \
*(TYPEE *)(vd + H(reg_off)) = val; \
}
@@ -4018,7 +4018,7 @@ static void sve_##NAME##_tlb(CPUARMState *env, void *vd,
intptr_t reg_off, \
target_ulong addr, uintptr_t ra) \
{ \
TYPEM val = *(TYPEE *)(vd + H(reg_off)); \
- TLB(env, addr, BSWAP(val), ra); \
+ TLB(env, useronly_clean_ptr(addr), BSWAP(val), ra); \
}
#define DO_LD_PRIM_1(NAME, H, TE, TM) \
@@ -4152,6 +4152,19 @@ static bool sve_probe_page(SVEHostPage *info, bool
nofault,
int flags;
addr += mem_off;
+
+ /*
+ * User-only currently always issues with TBI. See the comment
+ * above useronly_clean_ptr. Usually we clean this top byte away
+ * during translation, but we can't do that for e.g. vector + imm
+ * addressing modes.
+ *
+ * We currently always enable TBI for user-only, and do not provide
+ * a way to turn it off. So clean the pointer unconditionally here,
+ * rather than look it up here, or pass it down from above.
+ */
+ addr = useronly_clean_ptr(addr);
+
flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault,
&info->host, retaddr);
info->flags = flags;
--
2.20.1
- [PATCH v6 25/42] target/arm: Implement helper_mte_check1, (continued)
- [PATCH v6 25/42] target/arm: Implement helper_mte_check1, Richard Henderson, 2020/03/12
- [PATCH v6 26/42] target/arm: Implement helper_mte_checkN, Richard Henderson, 2020/03/12
- [PATCH v6 27/42] target/arm: Add helper_mte_check_zva, Richard Henderson, 2020/03/12
- [PATCH v6 28/42] target/arm: Use mte_checkN for sve unpredicated loads, Richard Henderson, 2020/03/12
- [PATCH v6 29/42] target/arm: Use mte_checkN for sve unpredicated stores, Richard Henderson, 2020/03/12
- [PATCH v6 30/42] target/arm: Use mte_check1 for sve LD1R, Richard Henderson, 2020/03/12
- [PATCH v6 32/42] target/arm: Add mte helpers for sve scalar + int stores, Richard Henderson, 2020/03/12
- [PATCH v6 34/42] target/arm: Handle TBI for sve scalar + int memory ops, Richard Henderson, 2020/03/12
- [PATCH v6 31/42] target/arm: Add mte helpers for sve scalar + int loads, Richard Henderson, 2020/03/12
- [PATCH v6 33/42] target/arm: Add mte helpers for sve scalar + int ff/nf loads, Richard Henderson, 2020/03/12
- [PATCH v6 36/42] target/arm: Complete TBI clearing for user-only for SVE,
Richard Henderson <=
- [PATCH v6 38/42] target/arm: Set PSTATE.TCO on exception entry, Richard Henderson, 2020/03/12
- [PATCH v6 37/42] target/arm: Implement data cache set allocation tags, Richard Henderson, 2020/03/12
- [PATCH v6 39/42] target/arm: Enable MTE, Richard Henderson, 2020/03/12
- [PATCH v6 40/42] target/arm: Cache the Tagged bit for a page in MemTxAttrs, Richard Henderson, 2020/03/12
- [PATCH v6 41/42] target/arm: Create tagged ram when MTE is enabled, Richard Henderson, 2020/03/12
- [PATCH v6 42/42] target/arm: Add allocation tag storage for system mode, Richard Henderson, 2020/03/12
- [PATCH v6 35/42] target/arm: Add mte helpers for sve scatter/gather memory ops, Richard Henderson, 2020/03/12