[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v6 30/42] target/arm: Use mte_check1 for sve LD1R
From: |
Richard Henderson |
Subject: |
[PATCH v6 30/42] target/arm: Use mte_check1 for sve LD1R |
Date: |
Thu, 12 Mar 2020 12:42:07 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-sve.c | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 49d2e68564..e5d12edd55 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4850,16 +4850,16 @@ static bool trans_LD1RQ_zpri(DisasContext *s,
arg_rpri_load *a)
/* Load and broadcast element. */
static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a)
{
- if (!sve_access_check(s)) {
- return true;
- }
-
unsigned vsz = vec_full_reg_size(s);
unsigned psz = pred_full_reg_size(s);
unsigned esz = dtype_esz[a->dtype];
unsigned msz = dtype_msz(a->dtype);
TCGLabel *over = gen_new_label();
- TCGv_i64 temp;
+ TCGv_i64 temp, clean_addr;
+
+ if (!sve_access_check(s)) {
+ return true;
+ }
/* If the guarding predicate has no bits set, no load occurs. */
if (psz <= 8) {
@@ -4880,9 +4880,11 @@ static bool trans_LD1R_zpri(DisasContext *s,
arg_rpri_load *a)
}
/* Load the data. */
- temp = tcg_temp_new_i64();
- tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz);
- tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s),
+ temp = read_cpu_reg_sp(s, a->rn, true);
+ tcg_gen_addi_i64(temp, temp, a->imm << msz);
+ clean_addr = gen_mte_check1(s, temp, false, true, msz);
+
+ tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s),
s->be_data | dtype_mop[a->dtype]);
/* Broadcast to *all* elements. */
--
2.20.1
- [PATCH v6 18/42] target/arm: Simplify DC_ZVA, (continued)
- [PATCH v6 18/42] target/arm: Simplify DC_ZVA, Richard Henderson, 2020/03/12
- [PATCH v6 22/42] target/arm: Move regime_tcr to internals.h, Richard Henderson, 2020/03/12
- [PATCH v6 19/42] target/arm: Implement the LDGM, STGM, STZGM instructions, Richard Henderson, 2020/03/12
- [PATCH v6 23/42] target/arm: Add gen_mte_check1, Richard Henderson, 2020/03/12
- [PATCH v6 24/42] target/arm: Add gen_mte_checkN, Richard Henderson, 2020/03/12
- [PATCH v6 25/42] target/arm: Implement helper_mte_check1, Richard Henderson, 2020/03/12
- [PATCH v6 26/42] target/arm: Implement helper_mte_checkN, Richard Henderson, 2020/03/12
- [PATCH v6 27/42] target/arm: Add helper_mte_check_zva, Richard Henderson, 2020/03/12
- [PATCH v6 28/42] target/arm: Use mte_checkN for sve unpredicated loads, Richard Henderson, 2020/03/12
- [PATCH v6 29/42] target/arm: Use mte_checkN for sve unpredicated stores, Richard Henderson, 2020/03/12
- [PATCH v6 30/42] target/arm: Use mte_check1 for sve LD1R,
Richard Henderson <=
- [PATCH v6 32/42] target/arm: Add mte helpers for sve scalar + int stores, Richard Henderson, 2020/03/12
- [PATCH v6 34/42] target/arm: Handle TBI for sve scalar + int memory ops, Richard Henderson, 2020/03/12
- [PATCH v6 31/42] target/arm: Add mte helpers for sve scalar + int loads, Richard Henderson, 2020/03/12
- [PATCH v6 33/42] target/arm: Add mte helpers for sve scalar + int ff/nf loads, Richard Henderson, 2020/03/12
- [PATCH v6 36/42] target/arm: Complete TBI clearing for user-only for SVE, Richard Henderson, 2020/03/12
- [PATCH v6 38/42] target/arm: Set PSTATE.TCO on exception entry, Richard Henderson, 2020/03/12
- [PATCH v6 37/42] target/arm: Implement data cache set allocation tags, Richard Henderson, 2020/03/12
- [PATCH v6 39/42] target/arm: Enable MTE, Richard Henderson, 2020/03/12
- [PATCH v6 40/42] target/arm: Cache the Tagged bit for a page in MemTxAttrs, Richard Henderson, 2020/03/12
- [PATCH v6 41/42] target/arm: Create tagged ram when MTE is enabled, Richard Henderson, 2020/03/12