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Re: [Qemu-arm] [Qemu-devel] [PATCH v2 05/14] target/arm/helper: zcr: Add
Re: [Qemu-arm] [Qemu-devel] [PATCH v2 05/14] target/arm/helper: zcr: Add build bug next to value range assumption
Mon, 24 Jun 2019 17:03:08 +0100
On Mon, Jun 24, 2019 at 12:30:37PM +0100, Andrew Jones wrote:
> On Mon, Jun 24, 2019 at 12:05:07PM +0100, Dave Martin wrote:
> > On Fri, Jun 21, 2019 at 05:34:13PM +0100, Andrew Jones wrote:
> > The purpose of this check should probably at least be described in a
> > comment -- i.e., what actually depends on this?
> I was thinking the already present "Bits other than [3:0] are RAZ/WI."
> explained that, but how about this for an improvement?
> * Only the lowest 4 bits of ZCR_ELx may be used to constrain the vector
> * length, the rest of the bits are RAZ/WI. Since the vector length of
> * 128-bits (1 in quadwords) is represented as zero in ZCR_ELx, and all
> * vector lengths are represented as their length in quadwords minus 1,
> * then four bits allow up to quadword 16 to be selected.
No, maybe the existing comment is enough.
I thought there might be more code elsewhere that assumes that checks
sve_max_vq <= ARM_MAX_VQ then then assumes that sve_max_vq <= 16. But
if not, we probably don't need an additional comment here.
I haven't tried to understand all the code in the series beyond the
user/kernel interactions, so maybe I was just paranoid.
Re: [Qemu-arm] [PATCH v2 05/14] target/arm/helper: zcr: Add build bug next to value range assumption, Auger Eric, 2019/06/26
Re: [Qemu-arm] [PATCH v2 05/14] target/arm/helper: zcr: Add build bug next to value range assumption, Richard Henderson, 2019/06/26
[Qemu-arm] [PATCH v2 06/14] target/arm: Allow SVE to be disabled via a CPU property, Andrew Jones, 2019/06/21
- Re: [Qemu-arm] [PATCH v2 02/14] target/arm/cpu: Ensure we can use the pmu with kvm, (continued)