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[Qemu-arm] [PATCH 07/10] target/arm: Implement HCR.PTW
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 07/10] target/arm: Implement HCR.PTW |
Date: |
Fri, 12 Oct 2018 15:42:32 +0100 |
If the HCR_EL2 PTW virtualizaiton configuration register bit
is set, then this means that a stage 2 Permission fault must
be generated if a stage 1 translation table access is made
to an address that is mapped as Device memory in stage 2.
Implement this.
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 78d05fe1e57..b5752d52dd1 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9134,9 +9134,20 @@ static hwaddr S1_ptw_translate(CPUARMState *env,
ARMMMUIdx mmu_idx,
hwaddr s2pa;
int s2prot;
int ret;
+ ARMCacheAttrs cacheattrs = {};
+ ARMCacheAttrs *pcacheattrs = NULL;
+
+ if (env->cp15.hcr_el2 & HCR_PTW) {
+ /*
+ * PTW means we must fault if this S1 walk touches S2 Device
+ * memory; otherwise we don't care about the attributes and can
+ * save the S2 translation the effort of computing them.
+ */
+ pcacheattrs = &cacheattrs;
+ }
ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
- &txattrs, &s2prot, &s2size, fi, NULL);
+ &txattrs, &s2prot, &s2size, fi, pcacheattrs);
if (ret) {
assert(fi->type != ARMFault_None);
fi->s2addr = addr;
@@ -9144,6 +9155,14 @@ static hwaddr S1_ptw_translate(CPUARMState *env,
ARMMMUIdx mmu_idx,
fi->s1ptw = true;
return ~0;
}
+ if (pcacheattrs && (pcacheattrs->attrs & 0xf0) == 0) {
+ /* Access was to Device memory: generate Permission fault */
+ fi->type = ARMFault_Permission;
+ fi->s2addr = addr;
+ fi->stage2 = true;
+ fi->s1ptw = true;
+ return ~0;
+ }
addr = s2pa;
}
return addr;
--
2.19.0
- [Qemu-arm] [PATCH 01/10] target/arm: Improve debug logging of AArch32 exception return, (continued)
- [Qemu-arm] [PATCH 01/10] target/arm: Improve debug logging of AArch32 exception return, Peter Maydell, 2018/10/12
- [Qemu-arm] [PATCH 02/10] target/arm: Make switch_mode() file-local, Peter Maydell, 2018/10/12
- [Qemu-arm] [PATCH 03/10] target/arm: Implement HCR.FB, Peter Maydell, 2018/10/12
- [Qemu-arm] [PATCH 04/10] target/arm: Implement HCR.DC, Peter Maydell, 2018/10/12
- [Qemu-arm] [PATCH 05/10] target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set, Peter Maydell, 2018/10/12
- [Qemu-arm] [PATCH 07/10] target/arm: Implement HCR.PTW,
Peter Maydell <=
- [Qemu-arm] [PATCH 06/10] target/arm: Implement HCR.VI and VF, Peter Maydell, 2018/10/12
- [Qemu-arm] [PATCH 09/10] target/arm: Get IL bit correct for v7 syndrome values, Peter Maydell, 2018/10/12
- [Qemu-arm] [PATCH 10/10] target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode, Peter Maydell, 2018/10/12
- [Qemu-arm] [PATCH 08/10] target/arm: New utility function to extract EC from syndrome, Peter Maydell, 2018/10/12