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[Qemu-arm] [PATCH 04/10] target/arm: Implement HCR.DC
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 04/10] target/arm: Implement HCR.DC |
Date: |
Fri, 12 Oct 2018 15:42:29 +0100 |
The HCR.DC virtualization configuration register bit has the
following effects:
* SCTLR.M behaves as if it is 0 for all purposes except
direct reads of the bit
* HCR.VM behaves as if it is 1 for all purposes except
direct reads of the bit
* the memory type produced by the first stage of the EL1&EL0
translation regime is Normal Non-Shareable,
Inner Write-Back Read-Allocate Write-Allocate,
Outer Write-Back Read-Allocate Write-Allocate.
Implement this behaviour.
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index cbec6844a44..84b40031b6f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2300,13 +2300,15 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t
value,
* * The Non-secure TTBCR.EAE bit is set to 1
* * The implementation includes EL2, and the value of HCR.VM is 1
*
+ * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
+ *
* ATS1Hx always uses the 64bit format (not supported yet).
*/
format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
if (arm_feature(env, ARM_FEATURE_EL2)) {
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
- format64 |= env->cp15.hcr_el2 & HCR_VM;
+ format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC);
} else {
format64 |= arm_current_el(env) == 2;
}
@@ -8711,7 +8713,8 @@ static inline bool
regime_translation_disabled(CPUARMState *env,
}
if (mmu_idx == ARMMMUIdx_S2NS) {
- return (env->cp15.hcr_el2 & HCR_VM) == 0;
+ /* HCR.DC means HCR.VM behaves as 1 */
+ return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0;
}
if (env->cp15.hcr_el2 & HCR_TGE) {
@@ -8721,6 +8724,12 @@ static inline bool
regime_translation_disabled(CPUARMState *env,
}
}
+ if ((env->cp15.hcr_el2 & HCR_DC) &&
+ (mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1)) {
+ /* HCR.DC means SCTLR_EL1.M behaves as 0 */
+ return true;
+ }
+
return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
}
@@ -10701,6 +10710,16 @@ static bool get_phys_addr(CPUARMState *env,
target_ulong address,
/* Combine the S1 and S2 cache attributes, if needed */
if (!ret && cacheattrs != NULL) {
+ if (env->cp15.hcr_el2 & HCR_DC) {
+ /*
+ * HCR.DC forces the first stage attributes to
+ * Normal Non-Shareable,
+ * Inner Write-Back Read-Allocate Write-Allocate,
+ * Outer Write-Back Read-Allocate Write-Allocate.
+ */
+ cacheattrs->attrs = 0xff;
+ cacheattrs->shareability = 0;
+ }
*cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2);
}
--
2.19.0
- [Qemu-arm] [PATCH 00/10] target/arm: more HCR bits, improve syndrome reporting, Peter Maydell, 2018/10/12
- [Qemu-arm] [PATCH 01/10] target/arm: Improve debug logging of AArch32 exception return, Peter Maydell, 2018/10/12
- [Qemu-arm] [PATCH 02/10] target/arm: Make switch_mode() file-local, Peter Maydell, 2018/10/12
- [Qemu-arm] [PATCH 03/10] target/arm: Implement HCR.FB, Peter Maydell, 2018/10/12
- [Qemu-arm] [PATCH 04/10] target/arm: Implement HCR.DC,
Peter Maydell <=
- [Qemu-arm] [PATCH 05/10] target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set, Peter Maydell, 2018/10/12
- [Qemu-arm] [PATCH 07/10] target/arm: Implement HCR.PTW, Peter Maydell, 2018/10/12
- [Qemu-arm] [PATCH 06/10] target/arm: Implement HCR.VI and VF, Peter Maydell, 2018/10/12
- [Qemu-arm] [PATCH 09/10] target/arm: Get IL bit correct for v7 syndrome values, Peter Maydell, 2018/10/12
- [Qemu-arm] [PATCH 10/10] target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode, Peter Maydell, 2018/10/12