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Re: [Qemu-arm] [PATCH 05/10] target/arm: Implement AArch32 HCR and HCR2
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] [PATCH 05/10] target/arm: Implement AArch32 HCR and HCR2 |
Date: |
Thu, 16 Aug 2018 10:02:55 +0100 |
On 16 August 2018 at 09:55, Luc Michel <address@hidden> wrote:
> On 8/14/18 2:42 PM, Peter Maydell wrote:
>> The AArch32 HCR and HCR2 registers alias HCR_EL2
>> bits [31:0] and [63:32]; implement them.
>>
>> Signed-off-by: Peter Maydell <address@hidden>
>> ---
>> target/arm/helper.c | 39 +++++++++++++++++++++++++++++++++++----
>> 1 file changed, 35 insertions(+), 4 deletions(-)
>>
>> diff --git a/target/arm/helper.c b/target/arm/helper.c
>> index b6412fe9d1f..9701e413859 100644
>> --- a/target/arm/helper.c
>> +++ b/target/arm/helper.c
>> @@ -3754,11 +3754,15 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
>> .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
>> .access = PL2_RW,
>> .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
>> - { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
>> + { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
>> .type = ARM_CP_NO_RAW,
>> .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
>> .access = PL2_RW,
>> - .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
>> + .type = ARM_CP_CONST, .resetvalue = 0 },
>> + { .name = "HCR2", .state = ARM_CP_STATE_AA32,
>> + .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
>> + .access = PL2_RW,
>> + .type = ARM_CP_CONST, .resetvalue = 0 },
> As for HACTLR2, shouldn't we avoid defining HCR2 for ARMv7?
Yes. I was working off the v8 register list and should have
cross-checked what was present in v7.
thanks
-- PMM
- Re: [Qemu-arm] [PATCH 08/10] target/arm: Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked), (continued)
- [Qemu-arm] [PATCH 03/10] target/arm: Implement RAZ/WI HACTLR2, Peter Maydell, 2018/08/14
- [Qemu-arm] [PATCH 01/10] target/arm: Correct typo in HAMAIR1 regdef name, Peter Maydell, 2018/08/14
- [Qemu-arm] [PATCH 05/10] target/arm: Implement AArch32 HCR and HCR2, Peter Maydell, 2018/08/14
- [Qemu-arm] [PATCH 04/10] target/arm: Implement AArch32 HVBAR, Peter Maydell, 2018/08/14
- [Qemu-arm] [PATCH 10/10] target/arm: Implement support for taking exceptions to Hyp mode, Peter Maydell, 2018/08/14
- [Qemu-arm] [PATCH 09/10] target/arm: Implement AArch32 ERET instruction, Peter Maydell, 2018/08/14
- [Qemu-arm] [PATCH 02/10] target/arm: Add missing .cp = 15 to HMAIR1 and HAMAIR1 regdefs, Peter Maydell, 2018/08/14