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Re: [lwip-devel] Using lwIP in Xilinx Gigabit System Reference Design (G

From: llandre
Subject: Re: [lwip-devel] Using lwIP in Xilinx Gigabit System Reference Design (GSRD)
Date: Wed, 25 Oct 2006 10:22:15 +0200
User-agent: Thunderbird (Windows/20060909)

Hi Sathya,

Technically I dont see anything that would prevent such an effort to happen. The key thing is to write the temac adapter that works with lwIP stack.
I agree with you if we just want a port that works. However if we need to get the best achievable performances - that's my case - I think the things are more complicated. IIUC, in fact, the GSRD project exploits all the BRAM memory to extend the PPC cache (16kB+16kB+32kB=64kB). This way all the stack code and data fit in the cache. This allows the processor to execute at maximum speed all the TCP/IP code and thus to handle a 800 Mb/s TCP connection over gigabit link. So my question is: is it possible to reduce the memory footprint required by lwIP in order to make it fit in 64kB?

Since the new version of lwIP does allow for hardware checksum computation, it should not be an issue to get the design working.
I agree.

If you have Treck adapter code, then you can model the lwIP solution along the same lines. Note that in order to get the Sockets API working you will need kernel features support and hence you might have to use the xilkernel that ships with EDK.

Alternately, if using RAW API (simpler to port than Sockets), then the port should be relatively simple.
As I said before I need to reduce the footprint as much as possible. So I'm going to use RAW API.


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