[Libreboot-dev] Potential new libreboot port - Gigabyte GA-G41M-ES2L

[Damien Zammit]

Hi folks,

After many months of work, I have completed a blobless coreboot port
from bare metal, the Gigabyte GA-G41M-ES2L.

I am writing to document all that I know about this board so that the
libreboot devs can hopefully determine if it is a valid libreboot candidate:

This board has a G41 northbridge, ICH7 southbridge, and ITE 8718F
superio. (I wrote the raminit for this chipset from scratch).

First of all, the vendor bios for this mainboard does *not* ship with a
Management Engine binary blob.  This likely means that the ME is
disabled on this board, or even better still - that the ME hardware is
not even present in the silicon.
However, note that the 4-series chipset has a model - Q45 - that does
support AMT.
Note also that the HECI (PCI device that exposes the ME status) is able
to be enabled on this board, but when queried for ME status, returns all
0x0.  I am fairly confident that this means that the ME is not working
on this board, but the HECI (pci interface that usually connects to the
ME) hardware is still wired up to the board for some reason.

When I compile coreboot as I would almost in a libreboot configuration
(without microcode updates, native VGA init and raminit, no ME blob, but
enable the HECI device in devicetree.cb), and boot into Debian 8, i get
the following output from (a patched) intelmetool:

$ sudo ./intelmetool
Good news, you have a `82801GB/GR (ICH7 Family) LPC Interface Bridge` so
ME is present but can be disabled.
RCBA at 0xfed1c000
MEI not hidden on PCI, checking if visible
MEI found: [8086:2e34] 4 Series Chipset HECI Controller

ME Status   : 0x0
ME Status 2 : 0x0

ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode      : NO
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Reset
ME: Current Operation State : Preboot
ME: Current Operation Mode  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : ROM Phase
ME: Power Management Event  : Clean Moff->Mx wake
ME: Progress Phase State    : BEGIN

PCI READ [bc] : 0x000000bc
ME: Extend Register not valid

ME seems okay on this board
ME: failed to become ready
WRITE    [00] : CB: 0x80040007
WRITE    [00] : CB: 0x000002ff
ME: failed to become ready
ME: GET FW VERSION message failed
ME: failed to become ready
ME: circular buffer full, resetting...
ME: failed to become ready
ME: message (5) too large for buffer (2)
ME: GET FWCAPS message failed
exiting

This output gives me a bit more confidence that the ME is not connected
or not working.  Since the status bytes are both 0x0, this means that
the HECI status either did not return valid bytes because there is no ME
hardware present, or the ME hardware is present and is in permanent
reset. (?)

For those who want more confidence, I suggest trying to enable the HECI
device on an X200 with libreboot and see if the same kind of status appears.

Okay, thats the ME side of things.

What about the board status:
The board boots grub in text mode and can boot Debian 8.


3 known outstanding issues:

- When VGA native init is enabled and both (2) sticks of ram are
populated, the board hangs in coreboot. :(  Current workaround: use only
1 stick of ram in channel 0.

- IRQ9 is broken, the linux kernel disables it. (no harm done)

- The onboard NIC (RTL 8169) is currently unresponsive on MSI interrupt.
Current workaround: use USB NIC dongle.


Flashing instructions:

There is a DualBIOS mechanism on this board which makes it very tricky
to flash externally.  You must flash BOTH chips one-by-one externally
with no ATX power applied to the board.

Internal flashing instructions: To be tested.

Regards,
Damien