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Re: Vulnerabilities in Synchronous IPC Designs

From: Kip Macy
Subject: Re: Vulnerabilities in Synchronous IPC Designs
Date: Fri, 6 Jun 2003 16:23:13 -0700 (PDT)

I would argue that this would place _more_ emphasis
on parameterization - otherwise you risk ending up
with an unmaintainable mess.

> in order to generate fully optimized IPC operations:
>   o The API implemented by the kernel (V2, X0, X2,
> V4, etc.)
>   o The architecture to compiled for (IA-32, IA-64,
> PowerPC, etc.)
>   o The CPU to optimize for (PentiumIII vs. Pentium4
> vs. Athlon,
>     Itanium vs. Itanium2, etc.)
>   o The kernel to optimize for (Pistachio, Hazelnut,
> Fiasco, P4,
>     various asm kernels)
>   o The kernel version to optimize for (various
> kernel versions can
>     have different costs for, e.g., register
> transfer)
> As such, there exist no simple mapping from input
> variables to IPC
> operations.  The mapping gets even more complex when
> you take into
> consideration the various semantics of RPC
> operations discussed in
> this thread (e.g., using pinned memory vs. retrying
> the RPC).
>       eSk
> --
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