how to force a second variable expansion?

[Robert P. J. Day]

  (ok, i'm getting embarrassed by asking what i'm sure are simple
questions, but i've been looking at this for the past couple of hours
and haven't got it to work.  argh.)

  i have a normally-straightforward macro to process subdirectories:

    define do-subdirs
    @for dir in ${SUBDIRS} ; do                    \
        ${MAKE} CF=$${$${dir}_CONFIG_FILE} -C $@ ; \  (clearly wrong)
                ??????????????????????????
    done
    endef

now, i can define my SUBDIRS variable, but i also want to define some
config file variables that should be passed when processing the
appropriate subdirectory:

    SUBDIRS = d1 d2 d3

    d2_CONFIG_FILE = fred
    d3_CONFIG_FILE = barney

    clean configure build:
        $(do-subdirs)


as you can guess, if i happen to be processing, say, directory "d2", i
want the make invocation to be:

    $ make CF=fred -C d2

in short, the "do-subdirs" needs to first construct the appropriate
config file variable name ("d2_CONFIG_FILE", based on the directory
being processed), then further evaluate that name to get its variable
value ("fred").

  i've tried various combinations of variable expansion methods and
nothing seems to give me what i'm after.  can i do this with just
variable references?  or do i need to resort to some form of "eval"?

rday

p.s.  the reference to the config file can be passed regardless of the
target being processed -- build, clean, configure.  it will just have
meaning only to the configure step, but it won't do any harm to any of
the others.