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[Discuss-gnuradio] [GSoC19] Weekly report of Verilog simulation phase 2

From: Bowen Hu
Subject: [Discuss-gnuradio] [GSoC19] Weekly report of Verilog simulation phase 2 week 1
Date: Mon, 8 Jul 2019 15:37:52 +0000

Hi all,

The following content is the abstract  of report, please find the full report at the link above.​
## Progress this week
I created a new block named verilog_axi_ii. This block is a sync block with a simplified AXI4-Stream interface. You can find this new block here.

In detail, I incorporated the functionality of the generate_verilator_file() into generate_so(). Because I found that I could do both things at once with just one Makefile.

I also finished and tested the Makefile template axi_module_cl.mk for the AXI-stream interface, this file could call Verilator to compile the Verilog file then generate the shared library. You can find this Makefile here. Here, in order to simplify the process, I fixed the module name generated by Verilator to Vaxi_module. User Verilog module should have following interface.

 * AXI signals:
 * ACLK               input
 * ARESETn            input
 * TVALID_IN          input
 * TREADY_IN          output
 * TVALID_OUT         output
 * TREADY_OUT         input
 * TDATA_IN[31:0]     input
 * TDATA_OUT[31:0]    output

I finished the template of the shared library code axi_module.h and axi_module.cpp, but I did not test them yet. The shared library interface is as below. You could find axi_module.h here and axi_module.cpp here.

void AXI_init();

void AXI_reset();

void AXI_transfer(const unsigned int &gr_input,
                  unsigned int &gr_output,
                  unsigned int &time);

void AXI_nop();

void AXI_close();

##Plan next week
I think I have completed the main part of this block. I plan to let verilog_axi_ii run next week and test it with a small Verilog module.


Best regards,​

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