|Subject:||Re: [Discuss-gnuradio] [GSoC19] Report of Verilog simulation evaluation 1|
|Date:||Mon, 1 Jul 2019 23:08:42 +0100|
|User-agent:||Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.1|
I'm glad that the project is going well! Congratulations on your progress so far.
When do you expect to have a block with an AXI FIFO working? I think that will be a really useful point for more people to try running the code and see what it looks like to run just a simple "copy" example.
On 01/07/2019 15:30, Bowen Hu wrote:
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