[Commit-gnuradio] r5936 - gnuradio/branches/developers/matt/u2f/top/u2_basic

[matt]

Author: matt
Date: 2007-07-11 14:13:29 -0600 (Wed, 11 Jul 2007)
New Revision: 5936

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Log:
output control lines handled by a setting reg, no longer directly on wb


Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-07-11 20:09:46 UTC (rev 5935)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-07-11 20:13:29 UTC (rev 5936)
@@ -296,11 +296,11 @@
    
    assign       s3_err = 1'b0;
    assign       s3_rty = 1'b0;
-
+   
    // GPIOs -- Slave #4
    wire         s4_ack_a, s4_ack_b, s4_ack_c, s4_ack_d;
    assign       s4_ack = s4_ack_a | s4_ack_b | s4_ack_c | s4_ack_d;
-
+   
    simple_gpio gpio_a(.clk_i(wb_clk),.rst_i(~wb_rst),
                      
.cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[0]),.adr_i(s4_adr[2]),.we_i(s4_we),
                      
.dat_i(s4_dat_o[7:0]),.dat_o(s4_dat_i[7:0]),.ack_o(s4_ack_a),
@@ -323,19 +323,9 @@
 
    assign       s4_err = 1'b0;
    assign       s4_rty = 1'b0;
-   
-   // Output control lines, SLAVE #5
-   wire [7:0]   clock_outs, serdes_outs, adc_outs, misc_outs;
-   assign       {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
-   assign       {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = 
serdes_outs[3:0];
-   assign       { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = adc_outs[3:0];
-   assign       {led2, led1} = misc_outs[1:0];
-   
-   wb_output_pins32 control_lines
-     
(.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(s5_dat_o),.wb_dat_o(s5_dat_i),
-      
.wb_we_i(s5_we),.wb_sel_i(s5_sel),.wb_stb_i(s5_stb),.wb_ack_o(s5_ack),.wb_cyc_i(s5_cyc),
-      .port_output( {clock_outs,serdes_outs,adc_outs,misc_outs} )  );
 
+   // Unused slave, #5
+   assign       s5_ack = s5_stb;
    assign       s5_err = 1'b0;
    assign       s5_rty = 1'b0;
 
@@ -354,7 +344,23 @@
    assign       s7_rty = 1'b0;
    assign       s7_dat_i = 32'd0;
 
-   ///////////////////////////////////////////////////////////////////////////
+   // Output control lines
+   wire [7:0]   clock_outs, serdes_outs, adc_outs, misc_outs;
+   assign       {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
+   assign       {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = 
serdes_outs[3:0];
+   assign       { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = adc_outs[3:0];
+   assign       {led2, led1} = misc_outs[1:0];
+   
+   setting_reg #(.my_addr(0)) sr_clk 
(.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
+                                     
.in(set_data),.out(clock_outs),.changed());
+   setting_reg #(.my_addr(1)) sr_ser 
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+                                     
.in(set_data),.out(serdes_outs),.changed());
+   setting_reg #(.my_addr(2)) sr_adc 
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+                                     .in(set_data),.out(adc_outs),.changed());
+   setting_reg #(.my_addr(3)) sr_led 
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+                                     .in(set_data),.out(misc_outs),.changed());
+
+   // /////////////////////////////////////////////////////////////////////////
    // DSP
    reg [13:0]   adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
    reg                  adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, 
adc_ovf_b_reg2;
@@ -389,7 +395,7 @@
    
    assign dsp_rst = wb_rst;
 
-   
/////////////////////////////////////////////////////////////////////////////////////
+   // 
///////////////////////////////////////////////////////////////////////////////////
    // SERDES
    serdes_tx serdes_tx
      (.clk(dsp_clk),.rst(dsp_rst),
@@ -397,7 +403,7 @@
       
.fifo_data_i(rd0_dat),.fifo_read_o(rd0_read),.fifo_done_o(rd0_done),.fifo_error_o(rd0_error),
       .fifo_ready_i(rd0_ready),.fifo_empty_i(rd0_empty)
       );
-
+   
    serdes_rx serdes_rx
      (.clk(dsp_clk),.rst(dsp_rst),
       
.ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
@@ -405,25 +411,27 @@
       .fifo_ready_i(wr0_ready),.fifo_full_i(wr0_full)
       );
    
+   
+   // 
/////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
-   wire [31:0] 
debug1={{1'b0,ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,wb_rst,dsp_rst},
-                       
{1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached},
-                       {8'hAF},
-                       {2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}};
-
-   wire [31:0] 
debug_wb={{iram_wr_we,ram_loader_done,clock_ready,iram_wr_ack,iram_wr_stb,ram_loader_rst,wb_rst,dsp_rst},
-                         {iram_rd_adr[15:8]},
-                         {iram_rd_adr[7:0]},
-                         {serdes_outs}};
-
-   assign      io_rx = ser_debug[31:16];
-   assign      io_tx = ser_debug[15:0];
- 
-   assign      debug = debug_wb;
+   wire [31:0] 
debug1={{1'b0,ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,wb_rst,dsp_rst},
+                      
{1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached},
+                      {8'hAF},
+                      {2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}};
    
-   assign      debug_clk[0] = wb_clk;
-   assign      debug_clk[1] = dsp_clk; 
+   wire [31:0] 
debug_wb={{iram_wr_we,ram_loader_done,clock_ready,iram_wr_ack,iram_wr_stb,ram_loader_rst,wb_rst,dsp_rst},
+                        {iram_rd_adr[15:8]},
+                        {iram_rd_adr[7:0]},
+                        {serdes_outs}};
    
+   assign      io_rx = ser_debug[31:16];
+   assign      io_tx = ser_debug[15:0];
+   
+   assign      debug = debug_wb;
+   
+   assign      debug_clk[0] = wb_clk;
+   assign      debug_clk[1] = dsp_clk; 
+   
 endmodule // u2_basic
 
 // Local Variables: