[Commit-gnuradio] r5918 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-07-05 18:52:06 -0600 (Thu, 05 Jul 2007)
New Revision: 5918

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
Log:
serdes model abstracted out into its own file


Modified: gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v       
2007-07-06 00:51:12 UTC (rev 5917)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v       
2007-07-06 00:52:06 UTC (rev 5918)
@@ -4,8 +4,8 @@
 
    reg clk, rst;
    wire ser_rx_clk, ser_tx_clk;
-   wire ser_rklsb, ser_rkmsb, ser_tklsb, ser_tkmsb, ser_rklsb_odd, 
ser_rkmsb_odd;
-   wire [15:0] ser_r, ser_t, ser_r_odd;
+   wire ser_rklsb, ser_rkmsb, ser_tklsb, ser_tkmsb;
+   wire [15:0] ser_r, ser_t;
    
    initial clk = 0;
    initial rst = 1;
@@ -28,6 +28,8 @@
    reg [8:0]   fl_tx, ll_tx;
    reg                read_go_tx, write_go_tx, clear_tx;
    wire        fdone_tx, ferror_tx;
+
+   reg                even;
    
    serdes_tx serdes_tx
      (.clk(clk),.rst(rst),
@@ -92,23 +94,11 @@
       );
 
    // Simulate the connection
-   assign      ser_rx_clk = ser_tx_clk;
+   serdes_model serdes_model
+     (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), 
.ser_t(ser_t),
+      .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), 
.ser_r(ser_t),
+      .even(even));
    
-   reg                even = 0;
-   
-   reg                hold_k;
-   reg [7:0]   hold_dat;
-   
-   always @(posedge clk) hold_k <= ser_tklsb;
-   always @(posedge clk) hold_dat <= ser_t[15:8];
-   assign      ser_rklsb_odd = hold_k;
-   assign      ser_rkmsb_odd = ser_tklsb;
-   assign      ser_r_odd = {ser_t[7:0], hold_dat};
-   
-   assign      ser_rkmsb = even ? ser_tkmsb : ser_rkmsb_odd;
-   assign      ser_rklsb = even ? ser_tklsb : ser_rklsb_odd;
-   assign      ser_r = even ? ser_t : ser_r_odd;
-
    // Fill the ram
    initial wb_en_rx <= 0;
    
@@ -132,6 +122,7 @@
         wb_adr <= wb_adr + 1;
       end // repeat (511)
       $display("Done entering Data into RAM\n");
+      even <= 0;
       repeat(10)
        @(posedge clk);
       write_go_rx <= 1;