[Commit-gnuradio] r5889 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-07-02 14:51:40 -0600 (Mon, 02 Jul 2007)
New Revision: 5889

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
Log:
changed a lot of 1XN to NX1 so we can view it in the output VCD


Modified: gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v     
2007-07-02 20:50:03 UTC (rev 5888)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v     
2007-07-02 20:51:40 UTC (rev 5889)
@@ -43,56 +43,53 @@
    );
 
    wire [7:0]   sel_a;
-   //wire       sel_a[0:7];
-
+   
    wire [2:0]   which_buf = wb_adr_i[13:11];   // address 15:14 selects the 
buffer pool
-   wire [8:0]  buf_addra = wb_adr_i[10:2];     // ignore address 1:0, 32-bit 
access only
- 
+   wire [8:0]   buf_addra = wb_adr_i[10:2];     // ignore address 1:0, 32-bit 
access only
+   
    decoder_3_8 dec(.sel(which_buf),.res(sel_a));
-
-   genvar      i;
-
-   wire [8:0]  fl[0:7];
-   wire [8:0]  ll[0:7];
-   wire [3:0]  step[0:7];
-   wire        read_go[0:7];
-   wire        write_go[0:7];
-   wire [1:0]  read_port[0:7];
-   wire [1:0]  write_port[0:7];
-   wire [2:0]  dummy[0:7];
-   wire        clear [0:7];       
-
-   // wire        done[0:7];
-   // wire        error[0:7];
-   wire [7:0]       done;
-   wire [7:0]      error;
-
-   wire        changed [0:7];
-
-   wire [31:0] buf_doa[0:7];
    
-   wire        buf_enb[0:7];
-   wire        buf_web[0:7];
-   wire [8:0]  buf_addrb[0:7];
-   wire [31:0] buf_dib[0:7];
-   wire [31:0] buf_dob[0:7];
+   genvar       i;
    
-   wire [31:0] wr_dat_i[0:7];
-   wire        wr_write_i[0:7];
-   wire        wr_done_i[0:7];
-   wire        wr_error_i[0:7];
-   wire        wr_ready_o[0:7];
-   wire        wr_full_o[0:7];
-
-   wire [31:0] rd_dat_o[0:7];
-   wire        rd_read_i[0:7];
-   wire        rd_done_i[0:7];
-   wire        rd_error_i[0:7];
-   wire        rd_ready_o[0:7];
-   wire        rd_empty_o[0:7];
+   wire [8:0]   fl[0:7];
+   wire [8:0]   ll[0:7];
+   wire [3:0]   step[0:7];
+   wire [7:0]   read_go;
+   wire [7:0]   write_go;
+   wire [1:0]   read_port[0:7];
+   wire [1:0]   write_port[0:7];
+   wire [2:0]   dummy[0:7];
+   wire         clear [0:7];       
    
-   assign      status = {error[7:0],done[7:0]};
+   wire [7:0]   done;
+   wire [7:0]   error;
+   wire [7:0]   changed;
    
+   wire [31:0]          buf_doa[0:7];
+   
+   wire [7:0]   buf_enb;
+   wire [7:0]   buf_web;
+   wire [8:0]   buf_addrb[0:7];
+   wire [31:0]          buf_dib[0:7];
+   wire [31:0]          buf_dob[0:7];
+   
+   wire [31:0]          wr_dat_i[0:7];
+   wire [7:0]   wr_write_i;
+   wire [7:0]   wr_done_i;
+   wire [7:0]   wr_error_i;
+   wire [7:0]   wr_ready_o;
+   wire [7:0]   wr_full_o;
+   
+   wire [31:0]          rd_dat_o[0:7];
+   wire [7:0]   rd_read_i;
+   wire [7:0]   rd_done_i;
+   wire [7:0]   rd_error_i;
+   wire [7:0]   rd_ready_o;
+   wire [7:0]   rd_empty_o;
+   
+   assign       status = {error[7:0],done[7:0]};
+
+   // Setting reg is {dummy[2:0], clear, read_port[1:0], write_port[1:0], 
write_go, read_go, step[3:0], ll[8:0], fl[8:0]};
    generate
       for(i=0;i<8;i=i+1)
        begin : gen_buffer