[Commit-gnuradio] r5888 - gnuradio/branches/developers/matt/u2f/models

[matt]

Author: matt
Date: 2007-07-02 14:50:03 -0600 (Mon, 02 Jul 2007)
New Revision: 5888

Added:
   gnuradio/branches/developers/matt/u2f/models/serdes_model.v
Modified:
   gnuradio/branches/developers/matt/u2f/models/cpld_model.v
Log:
new serdes channel model, compile fix on cpld model


Modified: gnuradio/branches/developers/matt/u2f/models/cpld_model.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/models/cpld_model.v   2007-07-02 
20:33:18 UTC (rev 5887)
+++ gnuradio/branches/developers/matt/u2f/models/cpld_model.v   2007-07-02 
20:50:03 UTC (rev 5888)
@@ -1,7 +1,7 @@
  
 module cpld_model
   (input aux_clk, input start, input mode, input done,
-   output dout, output sclk, output detached);
+   output dout, output reg sclk, output detached);
 
    reg [7:0] rom[0:65535];
 
@@ -9,8 +9,6 @@
    reg [7:0]  data;
    assign     dout = data[7];
 
-   reg               sclk;
-
    reg [2:0]  state, bitcnt;
    
    localparam IDLE = 3'd0;

Added: gnuradio/branches/developers/matt/u2f/models/serdes_model.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/models/serdes_model.v                 
        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/models/serdes_model.v 2007-07-02 
20:50:03 UTC (rev 5888)
@@ -0,0 +1,33 @@
+
+module serdes_model
+  (input ser_tx_clk,
+   input ser_tkmsb,
+   input ser_tklsb,
+   input [15:0] ser_t,
+   
+   output ser_rx_clk,
+   output ser_rkmsb,
+   output ser_rklsb,
+   output [15:0] ser_r,
+   
+   input even);
+   
+   wire [15:0] ser_r_odd;
+   wire  ser_rklsb_odd, ser_rkmsb_odd;   
+   
+   reg [7:0] hold_dat;
+   reg              hold_k;
+   
+   always @(posedge ser_tx_clk) hold_k <= ser_tklsb;
+   always @(posedge ser_tx_clk) hold_dat <= ser_t[15:8];
+   assign    ser_rklsb_odd = hold_k;
+   assign    ser_rkmsb_odd = ser_tklsb;
+   assign    ser_r_odd = {ser_t[7:0], hold_dat};
+   
+   // Set outputs
+   assign    ser_rx_clk = ser_tx_clk;
+   assign    ser_rkmsb = even ? ser_tkmsb : ser_rkmsb_odd;
+   assign    ser_rklsb = even ? ser_tklsb : ser_rklsb_odd;
+   assign    ser_r = even ? ser_t : ser_r_odd;
+   
+endmodule // serdes_model