[Commit-gnuradio] r5518 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-05-22 18:33:17 -0600 (Tue, 22 May 2007)
New Revision: 5518

Added:
   gnuradio/branches/developers/matt/u2f/control_lib/fifo_int_tb.v
Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
Log:
read side works


Modified: gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v        
2007-05-22 22:49:38 UTC (rev 5517)
+++ gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v        
2007-05-23 00:33:17 UTC (rev 5518)
@@ -9,8 +9,8 @@
    input [8:0] firstline,
    input [8:0] lastline,
    input [3:0] step,
-   input go,
-   input read,
+   input read_go,
+   input write_go,
    output done,
    
    // Buffer Interface
@@ -38,29 +38,63 @@
    // FIXME do we want to be able to interleave reads and writes?
    // FIXME do we want rd_ack or rd_req?
    
-   reg [8:0]     wr_addr, rd_addr;
+   reg [8:0] addr;
+   assign    addr_o = addr;
+   
+   wire      rd_en, wr_en;
+   
+   assign    dat_to_buf = wr_dat_i;
+   assign    rd_dat_o = dat_from_buf;
+   assign    en_o = rd_en | wr_en;
 
-   assign        dat_to_buf = wr_dat_i;
-   assign        rd_dat_o = dat_from_buf;
-   assign        en_o = 1'b1;
+   localparam IDLE = 3'd0;
+   localparam PRE_READ = 3'd1;
+   localparam READING = 3'd2;
+   localparam WRITING = 3'd3;
+
+   reg [3:0]  state;
    
    always @(posedge clk)
-     if(go)
-       wr_addr <= firstline;
-     else if(wr_write_i)
+     if(rst)
        begin
-         we_o <= 1'b1;
-         wr_addr <= wr_addr + step;
+         addr <= 0;
+         state <= IDLE;
        end
-     else
-       we_o <= 1'b0;
+     else 
+       case(state)
+        IDLE :
+          if(read_go)
+            begin
+               addr <= firstline;
+               state <= PRE_READ;
+            end
+          else if(write_go)
+            begin
+               addr <= firstline;
+               state <= WRITING;
+            end
+        
+        PRE_READ :
+          begin
+             state <= READING;
+             addr <= addr + 1;
+          end
 
-/*
-    always @(posedge clk)
-     if(rd_read_i)
-       if(rd_addr == lastline)
-        rd_done_o <= 1'b1;
-       else
-       */ 
+        READING :
+          if(rd_read_i)
+            begin
+               addr <= addr + 1;
+               if(addr == lastline + 9'd1)
+                 state <= IDLE;
+            end
+
+        WRITING :
+          state <= IDLE;
+       endcase // case(state)
+
+   assign rd_en = (state == PRE_READ) || ((state == READING) && rd_read_i);
+   assign rd_empty_o = (state == IDLE);
+   assign rd_ready_o = (state == READING);
    
+   
 endmodule // fifo_int

Added: gnuradio/branches/developers/matt/u2f/control_lib/fifo_int_tb.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/fifo_int_tb.v             
                (rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/fifo_int_tb.v     
2007-05-23 00:33:17 UTC (rev 5518)
@@ -0,0 +1,111 @@
+
+
+module fifo_int_tb ();
+
+   reg clk = 0;
+   reg rst = 1;
+
+   initial #100 rst = 0;
+   always #5 clk = ~clk;
+
+   wire en, we;
+   reg  read_go, write_go;
+   wire [8:0] addr;
+   wire [31:0]            fifo2buf, buf2fifo;
+   reg [8:0]      firstline, lastline;
+   wire [3:0]     step = 1;
+
+   wire [31:0]            rd_dat_o;
+   wire           rd_ready_o, rd_empty_o;
+   wire           rd_done_i = 0;
+   reg                    rd_read_i;
+   
+   fifo_int fifo_int
+     (.clk(clk),.rst(rst),
+      .firstline(firstline),.lastline(lastline),
+      .step(step),.read_go(read_go),.write_go(),.done(),
+   
+      // Buffer Interface
+      .en_o(en),.we_o(we),.addr_o(addr),
+      .dat_to_buf(fifo2buf),.dat_from_buf(buf2fifo),
+
+      // Write FIFO Interface
+      .wr_dat_i(), .wr_write_i(), .wr_done_i(), .wr_ready_o(), .wr_full_o(),
+   
+      // Read FIFO Interface
+      .rd_dat_o(rd_dat_o), .rd_read_i(rd_read_i), .rd_done_i(rd_done_i), 
.rd_ready_o(rd_ready_o), .rd_empty_o(rd_empty_o)
+      );
+
+   reg                    ram_en, ram_we;
+   reg [8:0]      ram_addr;
+   reg [31:0]     ram_data;
+   
+   buffer_2k buffer_2k
+     (.clka(clk), .ena(ram_en), .wea(ram_we), .addra(ram_addr), 
.dia(ram_data), .doa(),
+      .clkb(clk), .enb(en), .web(we), .addrb(addr), .dib(fifo2buf), 
.dob(buf2fifo)
+      );
+
+   initial
+     begin
+       ram_addr <= 0;
+       ram_data <= 0;
+       read_go <= 0;
+       write_go <= 0;
+       rd_read_i <=0;
+       @(negedge rst);
+       @(posedge clk);
+       ram_en <= 1;
+       ram_we <= 1;
+       @(posedge clk);
+       repeat (511)
+         begin
+            ram_addr <= ram_addr + 1;
+            ram_data <= ram_data + 1;
+            ram_en <= 1;
+            ram_we <= 1;
+            @(posedge clk);
+         end
+       @(posedge clk);
+       firstline <= 500;
+       @(posedge clk);
+       lastline <= 511;
+       @(posedge clk);
+       read_go <= 1;
+       @(posedge clk);
+       read_go <= 0;
+       @(posedge clk);
+       @(posedge clk);
+       @(posedge clk);
+       repeat (10)
+         begin
+            rd_read_i <= 1;
+            @(posedge clk);
+         end
+       repeat (10)
+         begin
+            rd_read_i <= 1;
+            @(posedge clk);
+            rd_read_i <= 0;
+            @(posedge clk);
+         end
+       repeat (10)
+         begin
+            rd_read_i <= 1;
+            @(posedge clk);
+            rd_read_i <= 0;
+            @(posedge clk);
+            @(posedge clk);
+         end
+       $finish;
+     end
+   
+   always @(posedge clk)
+     if(rd_read_i == 1'd1)
+       $display("FIFO OUT %d, FIFO RDY %d, FIFO EMPTY ",rd_dat_o, rd_ready_o, 
rd_empty_o);
+          
+   initial begin
+      $dumpfile("fifo_int_tb.vcd");
+      $dumpvars(0,fifo_int_tb);
+   end
+
+endmodule // fifo_int_tb