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[Commit-gnuradio] r5517 - in gnuradio/branches/developers/jcorgan/sar-fe
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From: |
jcorgan |
|
Subject: |
[Commit-gnuradio] r5517 - in gnuradio/branches/developers/jcorgan/sar-fe: config gr-sar-fe/src/fpga gr-sar-fe/src/fpga/lib gr-sar-fe/src/fpga/tb gr-sar-fe/src/fpga/top gr-sar-fe/src/python |
|
Date: |
Tue, 22 May 2007 16:49:39 -0600 (MDT) |
Author: jcorgan
Date: 2007-05-22 16:49:38 -0600 (Tue, 22 May 2007)
New Revision: 5517
Added:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/Makefile.am
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb.sav
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb.sh
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb.v
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb_wave.sh
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/config/grc_gr_sar_fe.m4
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/Makefile.am
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/dac_interface.v
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar.v
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_control.v
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_tx.v
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/top/usrp_sar.rbf
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/top/usrp_sar.v
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/sar_tx.py
Log:
Work in progress.
Modified: gnuradio/branches/developers/jcorgan/sar-fe/config/grc_gr_sar_fe.m4
===================================================================
--- gnuradio/branches/developers/jcorgan/sar-fe/config/grc_gr_sar_fe.m4
2007-05-22 22:46:18 UTC (rev 5516)
+++ gnuradio/branches/developers/jcorgan/sar-fe/config/grc_gr_sar_fe.m4
2007-05-22 22:49:38 UTC (rev 5517)
@@ -27,6 +27,7 @@
gr-sar-fe/src/fpga/Makefile \
gr-sar-fe/src/fpga/top/Makefile \
gr-sar-fe/src/fpga/lib/Makefile \
+ gr-sar-fe/src/fpga/tb/Makefile \
gr-sar-fe/src/lib/Makefile \
gr-sar-fe/src/python/Makefile \
gr-sar-fe/src/python/run_tests
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/Makefile.am
===================================================================
--- gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/Makefile.am
2007-05-22 22:46:18 UTC (rev 5516)
+++ gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/Makefile.am
2007-05-22 22:49:38 UTC (rev 5517)
@@ -21,4 +21,4 @@
include $(top_srcdir)/Makefile.common
-SUBDIRS = lib top
+SUBDIRS = lib top tb
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/dac_interface.v
===================================================================
---
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/dac_interface.v
2007-05-22 22:46:18 UTC (rev 5516)
+++
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/dac_interface.v
2007-05-22 22:49:38 UTC (rev 5517)
@@ -19,7 +19,7 @@
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
-`include "../toplevel/config.vh"
+`include "../top/config.vh"
module
dac_interface(clk_i,rst_i,ena_i,strobe_i,tx_i_i,tx_q_i,tx_data_o,tx_sync_o);
input clk_i;
@@ -27,16 +27,16 @@
input ena_i;
input strobe_i;
- input [15:0] tx_i_i;
- input [15:0] tx_q_i;
+ input [13:0] tx_i_i;
+ input [13:0] tx_q_i;
- output [15:0] tx_data_o;
+ output [13:0] tx_data_o;
output tx_sync_o;
`ifdef TX_RATE_MAX
wire clk128;
reg clk64_d;
- reg [15:0] tx_data_o;
+ reg [13:0] tx_data_o;
// Create a 128 MHz clock
dacpll pll128(.areset(rst_i),.inclk0(clk_i),.c0(clk128));
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar.v
===================================================================
--- gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar.v
2007-05-22 22:46:18 UTC (rev 5516)
+++ gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar.v
2007-05-22 22:49:38 UTC (rev 5517)
@@ -22,10 +22,10 @@
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
-module sar(clk_i,saddr_i,sdata_i,s_strobe_i,tx_rst_i,tx_enable_i,tx_strobe_i,
- tx_dac_i_o,tx_dac_q_o,
- rx_rst_i,rx_enable_i,rx_strobe_i,rx_strobe_o,
- rx_adc_i_i,rx_adc_q_i,rx_ech_i_o,rx_ech_q_o);
+module sar(clk_i,saddr_i,sdata_i,s_strobe_i,
+ tx_strobe_i,tx_dac_i_o,tx_dac_q_o,
+ rx_strobe_i,rx_adc_i_i,rx_adc_q_i,
+ rx_strobe_o,rx_ech_i_o,rx_ech_q_o);
// System interface
input clk_i; // Master clock @ 64 MHz
@@ -34,39 +34,37 @@
input s_strobe_i; // Configuration bus write
// Transmit subsystem
- input tx_rst_i; // Independent subsystem reset
- input tx_enable_i; // Turn on transmitter functionality
input tx_strobe_i; // Generate an transmitter output sample
- output [15:0] tx_dac_i_o; // I channel transmitter output to DAC
- output [15:0] tx_dac_q_o; // Q channel transmitter output to DAC
+ output [13:0] tx_dac_i_o; // I channel transmitter output to DAC
+ output [13:0] tx_dac_q_o; // Q channel transmitter output to DAC
// Receive subsystem
- input rx_rst_i; // Independent subsystem reset
- input rx_enable_i; // Turn on receiver functionality
input rx_strobe_i; // Indicates receive sample ready from ADC
- output rx_strobe_o; // Indicates output samples ready for Rx FIFO
input [15:0] rx_adc_i_i; // I channel input from ADC
input [15:0] rx_adc_q_i; // Q channel input from ADC
+ output rx_strobe_o; // Indicates output samples ready for Rx FIFO
output [15:0] rx_ech_i_o; // I channel processed echos to Rx FIFO
output [15:0] rx_ech_q_o; // Q channel processed echos to Rx FIFO
- wire [15:0] mag;
- wire [31:0] freq;
- wire [31:0] phs;
+ wire reset; // Master application reset
+
+ wire [13:0] mag; // temporary
+ wire [31:0] freq; // temporary
+ wire [31:0] phs; // temporary
sar_control controller
- (.clk_i(clk_i),.rst_i(rst_i),.ena_i(1'b1),
+ (.clk_i(clk_i),.rst_i(1'b0),.ena_i(1'b1),
.s_strobe_i(s_strobe_i),.saddr_i(saddr_i),.sdata_i(sdata_i),
- .mag_o(mag),.freq_o(freq),.phs_o(phs));
+ .reset_o(reset),.mag_o(mag),.freq_o(freq),.phs_o(phs));
sar_tx transmitter
- ( .clk_i(clk_i),.rst_i(tx_rst_i),.ena_i(tx_enable_i),
- .mag_i(mag),.freq_i(freq),.phs_i(phase),
+ ( .clk_i(clk_i),.rst_i(reset),.ena_i(1'b1),
+ .mag_i(mag),.freq_i(freq),.phs_i(phs),
.strobe_i(tx_strobe_i),.tx_i_o(tx_dac_i_o),.tx_q_o(tx_dac_q_o) );
sar_rx receiver
- ( .clk_i(clk_i),.rst_i(rx_rst_i),.ena_i(rx_enable_i),
+ ( .clk_i(clk_i),.rst_i(reset),.ena_i(1'b0),
.strobe_i(rx_strobe_i),.rx_in_i_i(rx_adc_i_i),.rx_in_q_i(rx_adc_q_i),
- .rx_i_o(rx_ech_i_o),.rx_q_o(rx_ech_q_o),.rx_strobe_o(rx_strobe_o) );
+ .rx_strobe_o(rx_strobe_o),.rx_i_o(rx_ech_i_o),.rx_q_o(rx_ech_q_o) );
endmodule // sar
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_control.v
===================================================================
---
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_control.v
2007-05-22 22:46:18 UTC (rev 5516)
+++
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_control.v
2007-05-22 22:49:38 UTC (rev 5517)
@@ -23,7 +23,7 @@
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
module sar_control(clk_i,rst_i,ena_i,saddr_i,sdata_i,s_strobe_i,
- mag_o, freq_o, phs_o);
+ reset_o,mag_o,freq_o,phs_o);
// System interface
input clk_i; // Master clock @ 64 MHz
@@ -34,13 +34,25 @@
input s_strobe_i; // Configuration bus write
// Configuration outputs
- output [15:0] mag_o;
+ output reset_o;
+ output [13:0] mag_o;
output [31:0] freq_o;
output [31:0] phs_o;
+ // Internal configuration
+ wire tx_ena;
+ wire rx_ena;
+ wire lp_ena;
+ wire dr_ena;
+ wire md_ena;
+ wire [1:0] chirps;
+
// Configuration from host
- setting_reg #(`FR_USER_0)
sr_mag(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(mag_o));
- setting_reg #(`FR_USER_1)
sr_freq(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(freq_o));
- setting_reg #(`FR_USER_2)
sr_phs(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(phs_o));
+ setting_reg #(`FR_USER_0)
sr_mode(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
+
.out({chirps,md_ena,dr_ena,lp_ena,rx_ena,tx_ena,reset_o}));
+
+ setting_reg #(`FR_USER_1)
sr_mag(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(mag_o));
+ setting_reg #(`FR_USER_2)
sr_freq(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(freq_o));
+ setting_reg #(`FR_USER_3)
sr_phs(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(phs_o));
endmodule // sar_control
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_tx.v
===================================================================
--- gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_tx.v
2007-05-22 22:46:18 UTC (rev 5516)
+++ gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_tx.v
2007-05-22 22:49:38 UTC (rev 5517)
@@ -30,16 +30,21 @@
input strobe_i;
// Configuration
- input [31:0] mag_i;
+ input [13:0] mag_i;
input [31:0] freq_i;
input [31:0] phs_i;
// Output
- output [15:0] tx_i_o;
- output [15:0] tx_q_o;
+ output [13:0] tx_i_o;
+ output [13:0] tx_q_o;
+ wire [15:0] cordic_i, cordic_q;
+
cordic_nco
nco(.clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(strobe_i),
- .mag_i(mag_i[15:0]),.freq_i(freq_i),.phs_i(phs_i),
- .data_i_o(tx_i_o),.data_q_o(tx_q_o));
+ .mag_i({2'b00,mag_i}),.freq_i(freq_i),.phs_i(phs_i),
+ .data_i_o(cordic_i),.data_q_o(cordic_q));
+
+ assign tx_i_o = cordic_i[15:2];
+ assign tx_q_o = cordic_q[15:2];
endmodule // sar_tx
Property changes on:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb
___________________________________________________________________
Name: svn:ignore
+ Makefile
Makefile.in
sar_tb
out
*.out*
*.vcd
Added:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/Makefile.am
===================================================================
---
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/Makefile.am
(rev 0)
+++
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/Makefile.am
2007-05-22 22:49:38 UTC (rev 5517)
@@ -0,0 +1,30 @@
+#
+# Copyright 2007 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+include $(top_srcdir)/Makefile.common
+
+EXTRA_DIST = \
+ sar_tb.v \
+ sar_tb.sav \
+ sar_tb.sh \
+ sar_tb_wave.sh
+
+MOSTLYCLEANFILES = *~ *.vcd *.out* sar_tb
Added:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb.sav
===================================================================
---
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb.sav
(rev 0)
+++
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb.sav
2007-05-22 22:49:38 UTC (rev 5517)
@@ -0,0 +1,21 @@
+*-20.630867 3880800 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 -1 -1 -1
address@hidden
+sar_tb.clk
+sar_tb.ena
+sar_tb.rst
+sar_tb.uut.reset
address@hidden
+-
address@hidden
+sar_tb.uut.mag[13:0]
+sar_tb.uut.freq[31:0]
+sar_tb.uut.phs[31:0]
address@hidden
+-
address@hidden
+sar_tb.uut.transmitter.strobe_i
address@hidden
+-
address@hidden
+sar_tb.uut.tx_dac_i_o[13:0]
+sar_tb.uut.tx_dac_q_o[13:0]
Added:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb.sh
===================================================================
--- gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb.sh
(rev 0)
+++ gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb.sh
2007-05-22 22:49:38 UTC (rev 5517)
@@ -0,0 +1,3 @@
+#!/bin/sh
+iverilog -y ../lib/ -y ../../../../usrp/fpga/sdr_lib \
+ sar_tb.v -o sar_tb && ./sar_tb > sar_tb.out
Property changes on:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb.sh
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb.v
===================================================================
--- gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb.v
(rev 0)
+++ gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb.v
2007-05-22 22:49:38 UTC (rev 5517)
@@ -0,0 +1,180 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2007 Corgan Enterprises LLC
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+//
+
+`timescale 1ns/1ps
+
+`include "../lib/sar.v"
+
+`define FR_SAR_MODE 7'd64
+`define bmFR_SAR_MODE_RESET 32'h0001
+
+`define FR_SAR_AMPL 7'd65
+`define FR_SAR_FREQ 7'd66
+`define FR_SAR_PHASE 7'd67
+
+module sar_tb;
+
+ // System bus
+ reg clk;
+ reg rst;
+ reg ena;
+
+ // Configuration bus
+ reg [6:0] saddr;
+ reg [31:0] sdata;
+ reg s_strobe;
+
+ // DAC bus
+ reg tx_strobe;
+ wire [13:0] tx_dac_i;
+ wire [13:0] tx_dac_q;
+
+ // ADC bus
+ reg rx_strobe;
+ reg [15:0] rx_adc_i;
+ reg [15:0] rx_adc_q;
+
+ // FIFO bus
+ wire fifo_strobe;
+ wire [15:0] fifo_i;
+ wire [15:0] fifo_q;
+
+ // Configuration shadow registers
+ reg [31:0] mode;
+
+ sar uut
+ (.clk_i(clk),.saddr_i(saddr),.sdata_i(sdata),.s_strobe_i(s_strobe),
+ .tx_strobe_i(tx_strobe),.tx_dac_i_o(tx_dac_i),.tx_dac_q_o(tx_dac_q),
+ .rx_strobe_i(rx_strobe),.rx_adc_i_i(rx_adc_i),.rx_adc_q_i(rx_adc_q),
+ .rx_strobe_o(fifo_strobe),.rx_ech_i_o(fifo_i),.rx_ech_q_o(fifo_q));
+
+ // Drive tx_strobe @ half clock rate
+ always @(posedge clk)
+ tx_strobe <= ~tx_strobe;
+
+ // Start up initialization
+ initial
+ begin
+ clk = 0;
+ rst = 0;
+ ena = 0;
+ saddr = 0;
+ sdata = 0;
+ s_strobe = 0;
+ tx_strobe = 0;
+ rx_strobe = 1;
+ rx_adc_i = 0;
+ rx_adc_q = 0;
+ mode = 0;
+
+ @(posedge clk);
+ rst = 1;
+ @(posedge clk);
+ rst = 0;
+ @(posedge clk);
+ ena = 1;
+ end
+
+ always
+ #5 clk <= ~clk;
+
+ initial
+ begin
+ //$monitor($time, " clk=%b rst=%b", clk, uut.reset);
+
+ $dumpfile("sar_tb.vcd");
+ $dumpvars(0, sar_tb);
+ end
+
+ // Test tasks
+ task write_cfg_register;
+ input [6:0] regno;
+ input [31:0] value;
+
+ begin
+ @(posedge clk);
+ saddr <= regno;
+ sdata <= value;
+ s_strobe <= 1'b1;
+ @(posedge clk);
+ s_strobe <= 0;
+ end
+ endtask // write_cfg_register
+
+ // Application reset line
+ task set_reset;
+ input reset;
+
+ begin
+ mode = reset ? (mode | `bmFR_SAR_MODE_RESET) : (mode &
~`bmFR_SAR_MODE_RESET);
+ write_cfg_register(`FR_SAR_MODE, mode);
+ end
+ endtask // reset
+
+ // Waveform amplitude
+ task set_amplitude;
+ input [13:0] amp;
+
+ begin
+ write_cfg_register(`FR_SAR_AMPL, amp);
+ end
+ endtask // set_amplitude
+
+ // Waveform frequency
+ task set_frequency;
+ input [31:0] freq;
+
+ begin
+ write_cfg_register(`FR_SAR_FREQ, freq);
+ end
+ endtask // frequency
+
+ // Waveform frequency
+ task set_phase;
+ input [31:0] phase;
+
+ begin
+ write_cfg_register(`FR_SAR_PHASE, phase);
+ end
+ endtask // frequency
+
+ // Test transmitter functionality
+ task test_tx;
+ input [5:0] degree;
+
+ begin
+ #20 set_reset(1);
+ #20 set_amplitude(14'h1FFF);
+ #20 set_frequency(32'h07FFFFFF);
+ #20 set_phase(0);
+ #20 set_reset(0);
+ #10000;
+ end
+ endtask // test_tx
+
+ // Execute tests
+ initial
+ begin
+ #20 test_tx(12);
+ #100 $finish;
+ end
+endmodule
+
Added:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb_wave.sh
===================================================================
---
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb_wave.sh
(rev 0)
+++
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb_wave.sh
2007-05-22 22:49:38 UTC (rev 5517)
@@ -0,0 +1,2 @@
+#!/bin/sh
+gtkwave sar_tb.vcd sar_tb.sav
Property changes on:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/tb/sar_tb_wave.sh
___________________________________________________________________
Name: svn:executable
+ *
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/top/usrp_sar.rbf
===================================================================
(Binary files differ)
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/top/usrp_sar.v
===================================================================
---
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/top/usrp_sar.v
2007-05-22 22:46:18 UTC (rev 5516)
+++
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/top/usrp_sar.v
2007-05-22 22:49:38 UTC (rev 5517)
@@ -95,14 +95,14 @@
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit Side
- wire [15:0] tx_i, tx_q;
- wire [15:0] tx_dac;
+ wire [13:0] tx_i, tx_q;
+ wire [13:0] tx_dac;
dac_interface dac(.clk_i(clk64),.rst_i(tx_dsp_reset),.ena_i(enable_tx),
.strobe_i(tx_sample_strobe),.tx_i_i(tx_i),.tx_q_i(tx_q),
.tx_data_o(tx_dac),.tx_sync_o(TXSYNC_A));
- assign tx_a = tx_dac[15:2];
+ assign tx_a = tx_dac;
// Wedge DAC #2 at zero
assign TXSYNC_B = 1'b0;
@@ -141,14 +141,11 @@
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Top level application
- sar sar
- (
.clk_i(clk64),.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
-
.tx_rst_i(tx_dsp_reset),.tx_enable_i(enable_tx),.tx_strobe_i(tx_sample_strobe),
- .tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q),
-
.rx_rst_i(rx_dsp_reset),.rx_enable_i(enable_rx),.rx_strobe_i(rx_sample_strobe),.rx_strobe_o(rx_strobe),
-
.rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q),.rx_ech_i_o(rx_buf_i),.rx_ech_q_o(rx_buf_q)
- );
-
+ sar sar (
.clk_i(clk64),.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
+ .tx_strobe_i(tx_sample_strobe),.tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q),
+
.rx_strobe_i(rx_sample_strobe),.rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q),
+ .rx_strobe_o(rx_strobe),.rx_ech_i_o(rx_buf_i),.rx_ech_q_o(rx_buf_q)
+ );
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Control Functions
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/sar_tx.py
===================================================================
--- gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/sar_tx.py
2007-05-22 22:46:18 UTC (rev 5516)
+++ gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/sar_tx.py
2007-05-22 22:49:38 UTC (rev 5517)
@@ -15,17 +15,21 @@
self.set_amplitude(32000)
def set_amplitude(self, amplitude):
- self.trans._write_fpga_reg(usrp.FR_USER_0, int(amplitude))
+ self.trans._write_fpga_reg(usrp.FR_USER_1, int(amplitude))
+ def reset(self):
+ self.trans._write_fpga_reg(usrp.FR_USER_0, 1);
+ self.trans._write_fpga_reg(usrp.FR_USER_0, 0);
+
def tune(self, freq):
ftw = int(freq*(2**32)/_tx_freq_divisor)
print "Frequency tuning word to FPGA is", ftw
- self.trans._write_fpga_reg(usrp.FR_USER_1, ftw)
+ self.trans._write_fpga_reg(usrp.FR_USER_2, ftw)
def set_phase(self, phase):
ptw = int(float(2**32)*phase/(2.0*math.pi))
print "Phase tuning word to FPGA is", ptw
- self.trans._write_fpga_reg(usrp.FR_USER_2, ptw)
+ self.trans._write_fpga_reg(usrp.FR_USER_3, ptw)
def start(self):
self.trans.start()
@@ -59,6 +63,7 @@
def test_transmit(options):
t = sar_tx()
+ t.reset()
t.set_amplitude(options.amplitude)
t.tune(options.frequency)
t.set_phase(options.phase)
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- [Commit-gnuradio] r5517 - in gnuradio/branches/developers/jcorgan/sar-fe: config gr-sar-fe/src/fpga gr-sar-fe/src/fpga/lib gr-sar-fe/src/fpga/tb gr-sar-fe/src/fpga/top gr-sar-fe/src/python,
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