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[Commit-gnuradio] r5249 - in gnuradio/branches/developers/thottelt: inba
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From: |
thottelt |
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Subject: |
[Commit-gnuradio] r5249 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations |
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Date: |
Sat, 5 May 2007 17:45:44 -0600 (MDT) |
Author: thottelt
Date: 2007-05-05 17:45:43 -0600 (Sat, 05 May 2007)
New Revision: 5249
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
Log:
chan_reader seems to be working, but still need more work
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-05-05 22:37:46 UTC (rev 5248)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-05-05 23:45:43 UTC (rev 5249)
@@ -1,8 +1,10 @@
module chan_fifo_reader
( reset, tx_clock, tx_strobe, adc_time, samples_format,
fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
- overrun, underrun ) ;
+ overrun, underrun, tx_empty ) ;
+ parameter MAX_PAYLOAD = 504 ;
+
input wire reset ;
input wire tx_clock ;
input wire tx_strobe ;
@@ -16,8 +18,10 @@
output reg [15:0] tx_i ;
output reg overrun ;
output reg underrun ;
+ output reg tx_empty ;
// Should not be needed if adc clock rate < tx clock rate
+ // Used only to debug
`define JITTER 5
//Samples format
@@ -27,173 +31,159 @@
// States
`define IDLE 4'd0
`define READ 4'd1
- `define HEADER1 4'd2
- `define HEADER2 4'd3
- `define TIMESTAMP1 4'd4
- `define TIMESTAMP2 4'd5
- `define WAIT 4'd6
- `define WAITSTROBE 4'd7
- `define SENDWAIT 4'd8
- `define SEND 4'd9
- `define FEED 4'd10
- `define DISCARD 4'd11
+ `define HEADER 4'd2
+ `define TIMESTAMP 4'd3
+ `define WAIT 4'd4
+ `define WAITSTROBE 4'd5
+ `define SENDWAIT 4'd6
+ `define SEND 4'd7
+ `define DISCARD 4'd8
- // State registers
- reg[3:0] reader_state;
- reg[3:0] reader_next_state;
+ /* State registers */
+ reg [3:0] reader_state;
+ reg [3:0] reader_next_state;
- //Variables
- reg[8:0] payload_len;
- reg[8:0] read_len;
- reg[31:0] timestamp;
- reg burst;
- reg qsample;
- always @(posedge tx_clock)
- begin
- if (reset)
+
+ reg [8:0] payload_len;
+ reg [8:0] read_len;
+ reg [31:0] timestamp;
+ reg burst;
+
+ always @(posedge tx_clock)
+ begin
+ if (reset)
begin
- reader_state <= `IDLE;
- reader_next_state <= `IDLE;
- rdreq <= 0;
- skip <= 0;
- overrun <= 0;
- underrun <= 0;
- burst <= 0;
- qsample <= 1;
- end
+ reader_state <= `IDLE;
+ reader_next_state <= `IDLE;
+ rdreq <= 0;
+ skip <= 0;
+ overrun <= 0;
+ underrun <= 0;
+ burst <= 0;
+ tx_empty <= 1;
+ end
else
- begin
+ begin
reader_state = reader_next_state;
+
case (reader_state)
`IDLE:
- begin
- if (pkt_waiting == 1)
- begin
- reader_next_state <= `READ;
- rdreq <= 1;
- underrun <= 0;
- end
- else if (burst == 1)
+ begin
+ if (pkt_waiting == 1)
+ begin
+ reader_next_state <= `READ;
+ rdreq <= 1;
+ underrun <= 0;
+ end
+ else if (burst == 1)
underrun <= 1;
- end
+ end
- // Just wait for the fifo data to arrive
+ /* Just wait for the fifodata to show up */
`READ:
- begin
- reader_next_state <= `HEADER1;
- end
+ begin
+ reader_next_state <= `HEADER;
+ end
- // First part of the header
- `HEADER1:
- begin
- reader_next_state <= `HEADER2;
+ /* Process header */
+ `HEADER:
+ begin
+ reader_next_state <= `TIMESTAMP;
- //Check Start burst flag
- if (fifodata[3] == 1)
- burst <= 1;
+ //Check Start burst flag
+ if (fifodata[3] == 1)
+ burst <= 1;
- if (fifodata[4] == 1)
- burst <= 0;
- end
+ if (fifodata[4] == 1)
+ burst <= 0;
+
+ payload_len <= (fifodata & 16'h1FF) ;
+ read_len <= 0;
+
+ rdreq <= 0;
+ end
- // Read payload length
- `HEADER2:
- begin
- payload_len <= (fifodata & 16'h1FF);
- read_len <= 9'd0;
- reader_next_state <= `TIMESTAMP1;
- end
-
- `TIMESTAMP1:
- begin
- timestamp <= {fifodata, 16'b0};
- rdreq <= 0;
- reader_next_state <= `TIMESTAMP2;
- end
-
- `TIMESTAMP2:
- begin
- timestamp <= timestamp + fifodata;
+ `TIMESTAMP:
+ begin
+ timestamp <= fifodata;
reader_next_state <= `WAIT;
- end
+ end
- // Decide if we wait, send or discard samples
+ // Decide if we wait, send or discard samples
`WAIT:
- begin
+ begin
// Wait a little bit more
- if (timestamp > adc_clock + `JITTER)
- reader_next_state <= `WAIT;
+ if (timestamp > adc_time + `JITTER)
+ reader_next_state <= `WAIT;
// Let's send it
- else if ((timestamp < adc_clock + `JITTER
- && timestamp > adc_clock)
- || timestamp == 32'hFFFFFFFF)
- begin
- reader_next_state <= `WAITSTROBE;
- end
+ else if ((timestamp < adc_time + `JITTER
+ && timestamp > adc_time)
+ || timestamp == 32'hFFFFFFFF)
+ reader_next_state <= `WAITSTROBE;
// Outdated
- else if (timestamp < adc_clock)
- begin
- reader_next_state <= `DISCARD;
- skip <= 1;
+ else if (timestamp < adc_time)
+ begin
+ reader_next_state <= `DISCARD;
+ skip <= 1;
end
- end
+ end
- // Wait for the transmit chain to be ready
+ // Wait for the transmit chain to be ready
`WAITSTROBE:
- begin
- // If end of payload...
- if (read_len == payload_len)
- begin
- reader_next_state <= `DISCARD;
- skip <= (payload_len < 508);
- end
+ begin
+ // If end of payload...
+ if (read_len == payload_len)
+ begin
+ reader_next_state <= `DISCARD;
+ skip <= (payload_len < MAX_PAYLOAD);
+ end
- if (tx_strobe == 1)
- reader_next_state <= `SENDWAIT;
- end
+ if (tx_strobe == 1)
+ begin
+ reader_next_state <= `SENDWAIT;
+ rdreq <= 1;
+ end
+ end
`SENDWAIT:
- begin
- rdreq <= 1;
- reader_next_state <= `SEND;
- end
+ begin
+ reader_next_state <= `SEND;
+ rdreq <= 0;
+ end
- // Send the samples to the tx_chain
+ // Send the samples to the tx_chain
`SEND:
- begin
- reader_next_state <= `WAITSTROBE;
- rdreq <= 0;
- read_len <= read_len + 2;
- case(samples_format)
- `QI16:
- begin
- tx_q <= qsample ? fifodata : 16'bZ;
- tx_i <= ~qsample ? fifodata : 16'bZ;
- qsample <= ~ qsample;
- end
+ begin
+ reader_next_state <= `WAITSTROBE;
+ read_len <= read_len + 4;
+ case(samples_format)
+ `QI16:
+ begin
+ tx_q <= fifodata & 16'hFFFF;
+ tx_i <= fifodata & 32'hFFFF0000;
+ end
+
+ // Assume 16 bits complex samples by default
default:
- begin
- // Assume 16 bits complex samples by default
- $display ("Error unknown samples format");
- tx_q <= qsample ? fifodata : 16'bZ;
- tx_i <= ~qsample ? fifodata : 16'bZ;
- qsample <= ~ qsample;
- end
- endcase
- end
+ begin
+ tx_q <= fifodata & 16'hFFFF;
+ tx_i <= fifodata & 32'hFFFF0000;
+ end
+ endcase
+ end
`DISCARD:
- begin
- skip <= 0;
- reader_next_state <= `IDLE;
- end
+ begin
+ skip <= 0;
+ reader_next_state <= `IDLE;
+ end
default:
- begin
- $display ("Error unknown state");
- reader_state <= `IDLE;
- reader_next_state <= `IDLE;
- end
+ begin
+ $display ("Error unknown state");
+ reader_state <= `IDLE;
+ reader_next_state <= `IDLE;
+ end
endcase
end
end
Modified:
gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
2007-05-05 22:37:46 UTC (rev 5248)
+++ gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
2007-05-05 23:45:43 UTC (rev 5249)
@@ -3,7 +3,7 @@
// Inputs
reg reset;
reg txclock;
-reg [15:0] data_bus;
+reg [31:0] data_bus;
reg [31:0] ttime;
reg WR;
reg adcclock;
@@ -21,14 +21,14 @@
wire rdreq;
// fifo ouputs
-wire [15:0] fifodata;
+wire [31:0] fifodata;
wire pkt_waiting;
wire tx_strobe;
chan_fifo_reader chan0 (
.reset(reset),
.tx_clock(txclock),
- .adc_clock(ttime),
+ .adc_time(ttime),
.skip(skip),
.rdreq(rdreq),
.pkt_waiting(pkt_waiting),
@@ -52,7 +52,8 @@
.pkt_waiting(pkt_waiting),
.read_enable(rdreq),
.pkt_complete(pkt_complete),
- .skip_packet(skip)
+ .skip_packet(skip),
+ .have_space()
);
strobe_gen strobe_generator(
@@ -90,13 +91,10 @@
@(posedge txclock)
WR = 1'b1 ;
// Payload len
- if (i == 1)
+ if (i == 0)
data_bus = 32;
// First 16 bits of timestamp
- else if (i == 2)
- data_bus = 0;
- // 16 lower bits of timestamp
- else if (i == 3)
+ else if (i == 1)
data_bus = 1000;
else
data_bus = i ;
@@ -116,13 +114,10 @@
WR = 1'b1 ;
//Payload len
- if (i == 1)
+ if (i == 0)
data_bus = 16;
//First 16 bits of timestamp
- else if (i == 2)
- data_bus = 0;
- // 16 lower bits of timestamp
- else if (i == 3)
+ else if (i == 1)
data_bus = 1600;
else
data_bus = i ;
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-05-05
22:37:46 UTC (rev 5248)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-05-05
23:45:43 UTC (rev 5249)
@@ -259,13 +259,13 @@
Project_File_6 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178393232 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_7 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178408317 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_8 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178396255 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_9 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178234886 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_10 = ./chan_fifo_readers_test.v
-Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177273499 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178407738 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 1
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_11 = ../inband/usrp/fpga/megacells/fifo_1k.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232565 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_12 = ./usb_packet_fifo_test.v
@@ -309,6 +309,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1} {Z:/wc/simulations/usb_fifo_reader_test.v
0 1} {Z:/wc/simulations/tx_buffer_test.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/data_packet_fifo.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/chan_fifo_reader.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v 0 0}
+EditorState = {tabbed horizontal 1} {Z:/wc/simulations/tx_buffer_test.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/data_packet_fifo.v 0 1}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v 0 0}
{Z:/wc/simulations/usb_packet_fifo2_test.v 0 0}
{Z:/wc/simulations/chan_fifo_readers_test.v 0 0}
Project_Major_Version = 6
Project_Minor_Version = 1
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