[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Commit-gnuradio] r5248 - in gnuradio/branches/developers/jcorgan/sar/gr
|
From: |
jcorgan |
|
Subject: |
[Commit-gnuradio] r5248 - in gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src: fpga/lib fpga/rbf fpga/rbf/rev2 fpga/rbf/rev4 fpga/toplevel python |
|
Date: |
Sat, 5 May 2007 16:37:46 -0600 (MDT) |
Author: jcorgan
Date: 2007-05-05 16:37:46 -0600 (Sat, 05 May 2007)
New Revision: 5248
Added:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar.v
Removed:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/rbf/rev2/usrp_sar_max.rbf
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/rbf/rev4/usrp_sar_max.rbf
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/Makefile.am
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_rx.v
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_tx.v
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/rbf/Makefile.am
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/rbf/rev2/usrp_sar.rbf
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/rbf/rev4/usrp_sar.rbf
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/toplevel/Makefile.am
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/sar_tx.py
Log:
Refactored top-level fpga code, clean-up.
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/Makefile.am
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/Makefile.am
2007-05-05 20:50:56 UTC (rev 5247)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/Makefile.am
2007-05-05 22:37:46 UTC (rev 5248)
@@ -25,4 +25,6 @@
sar_tx.v \
sar_rx.v \
dac_interface.v \
- cordic_nco.v
\ No newline at end of file
+ cordic_nco.v
+
+MOSTLYCLEANFILES = *~
Added: gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar.v
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar.v
(rev 0)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar.v
2007-05-05 22:37:46 UTC (rev 5248)
@@ -0,0 +1,63 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2007 Corgan Enterprises LLC
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+//
+
+`include "../../../../usrp/firmware/include/fpga_regs_common.v"
+`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
+
+module sar(clk_i,saddr_i,sdata_i,s_strobe_i,tx_rst_i,tx_enable_i,tx_strobe_i,
+ tx_dac_i_o,tx_dac_q_o,
+ rx_rst_i,rx_enable_i,rx_strobe_i,rx_strobe_o,
+ rx_adc_i_i,rx_adc_q_i,rx_ech_i_o,rx_ech_q_o);
+
+ // System interface
+ input clk_i; // Master clock @ 64 MHz
+ input [6:0] saddr_i; // Configuration bus address
+ input [31:0] sdata_i; // Configuration bus data
+ input s_strobe_i; // Configuration bus write
+
+ // Transmit subsystem
+ input tx_rst_i; // Independent subsystem reset
+ input tx_enable_i; // Turn on transmitter functionality
+ input tx_strobe_i; // Generate an transmitter output sample
+ output [15:0] tx_dac_i_o; // I channel transmitter output to DAC
+ output [15:0] tx_dac_q_o; // Q channel transmitter output to DAC
+
+ // Receive subsystem
+ input rx_rst_i; // Independent subsystem reset
+ input rx_enable_i; // Turn on receiver functionality
+ input rx_strobe_i; // Indicates receive sample ready from ADC
+ output rx_strobe_o; // Indicates output samples ready for Rx FIFO
+ input [15:0] rx_adc_i_i; // I channel input from ADC
+ input [15:0] rx_adc_q_i; // Q channel input from ADC
+ output [15:0] rx_ech_i_o; // I channel processed echos to Rx FIFO
+ output [15:0] rx_ech_q_o; // Q channel processed echos to Rx FIFO
+
+ sar_tx transmitter
+ ( .clk_i(clk_i),.rst_i(tx_rst_i),.ena_i(tx_enable_i),
+ .saddr_i(saddr_i),.sdata_i(sdata_i),.s_strobe_i(s_strobe_i),
+ .strobe_i(tx_strobe_i),.tx_i_o(tx_dac_i_o),.tx_q_o(tx_dac_q_o) );
+
+ sar_rx receiver
+ ( .clk_i(clk_i),.rst_i(rx_rst_i),.ena_i(rx_enable_i),
+ .strobe_i(rx_strobe_i),.rx_in_i_i(rx_adc_i_i),.rx_in_q_i(rx_adc_q_i),
+ .rx_i_o(rx_ech_i_o),.rx_q_o(rx_ech_q_o),.rx_strobe_o(rx_strobe_o) );
+
+endmodule // sar
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_rx.v
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_rx.v
2007-05-05 20:50:56 UTC (rev 5247)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_rx.v
2007-05-05 22:37:46 UTC (rev 5248)
@@ -22,7 +22,7 @@
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
-module
sar_rx(clk_i,rst_i,ena_i,strobe_i,saddr_i,sdata_i,s_strobe_i,cpi_i,rx_in_i_i,rx_in_q_i,rx_i_o,rx_q_o,rx_strobe_o,debug_o);
+module
sar_rx(clk_i,rst_i,ena_i,strobe_i,saddr_i,sdata_i,s_strobe_i,rx_in_i_i,rx_in_q_i,rx_i_o,rx_q_o,rx_strobe_o);
input clk_i;
input rst_i;
input ena_i;
@@ -32,14 +32,12 @@
input [31:0] sdata_i;
input s_strobe_i;
- input [7:0] cpi_i;
input [15:0] rx_in_i_i;
input [15:0] rx_in_q_i;
output [15:0] rx_i_o;
output [15:0] rx_q_o;
output rx_strobe_o;
- output [15:0] debug_o;
// Just count up for debugging
reg [31:0] counter;
@@ -54,19 +52,12 @@
assign rx_i_o = ena_i ? counter[31:16] : 16'b0;
assign rx_q_o = ena_i ? counter[15:0] : 16'b0;
- assign debug_o = 16'hAA55;
// Temporarily we duplicate what master_control.v did to generate
decim_strobe
// so we can do receive debugging. Later we'll drive rx_strobe_o in bursts
to
// load receiver data into the rx fifo.
strobe_gen rx_strobe_gen
- ( .clock(clk_i),
- .reset(rst_i),
- .enable(ena_i),
- .rate(cpi_i),
- .strobe_in(strobe_i),
- .strobe(rx_strobe_o)
- );
+ (
.clock(clk_i),.reset(rst_i),.enable(ena_i),.rate(7),.strobe_in(strobe_i),.strobe(rx_strobe_o)
);
endmodule // sar_rx
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_tx.v
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_tx.v
2007-05-05 20:50:56 UTC (rev 5247)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_tx.v
2007-05-05 22:37:46 UTC (rev 5248)
@@ -22,7 +22,7 @@
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
-module
sar_tx(clk_i,rst_i,ena_i,strobe_i,saddr_i,sdata_i,s_strobe_i,tx_i_o,tx_q_o,debug_o);
+module
sar_tx(clk_i,rst_i,ena_i,strobe_i,saddr_i,sdata_i,s_strobe_i,tx_i_o,tx_q_o);
input clk_i;
input rst_i;
input ena_i;
@@ -34,7 +34,6 @@
output [15:0] tx_i_o;
output [15:0] tx_q_o;
- output [15:0] debug_o;
wire [31:0] mag, freq, phase;
setting_reg #(`FR_USER_0)
sr_mag(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(mag));
@@ -44,7 +43,5 @@
cordic_nco
nco(.clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(strobe_i),
.mag_i(mag[15:0]),.freq_i(freq),.phs_i(phase),
.data_i_o(tx_i_o),.data_q_o(tx_q_o));
-
- assign debug_o = 16'hAA55;
endmodule // sar_tx
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/rbf/Makefile.am
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/rbf/Makefile.am
2007-05-05 20:50:56 UTC (rev 5247)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/rbf/Makefile.am
2007-05-05 22:37:46 UTC (rev 5248)
@@ -24,9 +24,7 @@
datadir = $(prefix)/share/usrp
rbfs = rev2/usrp_sar.rbf \
- rev2/usrp_sar_max.rbf \
- rev4/usrp_sar.rbf \
- rev4/usrp_sar_max.rbf
+ rev4/usrp_sar.rbf
EXTRA_DIST = \
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/rbf/rev2/usrp_sar.rbf
===================================================================
(Binary files differ)
Deleted:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/rbf/rev2/usrp_sar_max.rbf
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/rbf/rev4/usrp_sar.rbf
===================================================================
(Binary files differ)
Deleted:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/rbf/rev4/usrp_sar_max.rbf
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/toplevel/Makefile.am
===================================================================
---
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/toplevel/Makefile.am
2007-05-05 20:50:56 UTC (rev 5247)
+++
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/toplevel/Makefile.am
2007-05-05 22:37:46 UTC (rev 5248)
@@ -29,3 +29,15 @@
usrp_sar.qsf \
usrp_sar_assignment_defaults.qdf \
usrp_sar.v
+
+MOSTLYCLEANFILES = \
+ db/* \
+ *.rpt \
+ *.summary \
+ *.rbf \
+ *.qws \
+ *.smsg \
+ *.done \
+ *.pin \
+ *.sof \
+ *~
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
===================================================================
---
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
2007-05-05 20:50:56 UTC (rev 5247)
+++
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
2007-05-05 22:37:46 UTC (rev 5248)
@@ -368,23 +368,25 @@
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition
-to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
+set_global_assignment -name VERILOG_FILE usrp_sar.v
set_global_assignment -name VERILOG_FILE dacpll.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/cordic_stage.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v
+set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
set_global_assignment -name VERILOG_FILE ../lib/sar_rx.v
set_global_assignment -name VERILOG_FILE ../lib/sar_tx.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_buffer.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/setting_reg.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/strobe_gen.v
+set_global_assignment -name VERILOG_FILE ../lib/sar.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/adc_interface.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/atr_delay.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/bidir_reg.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/clk_divider.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/bidir_reg.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/adc_interface.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/cordic_stage.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/gen_sync.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/io_pins.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/master_control.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_buffer.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE usrp_sar.v
\ No newline at end of file
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/setting_reg.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/strobe_gen.v
\ No newline at end of file
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
===================================================================
---
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
2007-05-05 20:50:56 UTC (rev 5247)
+++
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
2007-05-05 22:37:46 UTC (rev 5248)
@@ -20,8 +20,14 @@
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
-`include "config.vh"
+// Top level module for a full setup with DUCs and DDCs
+// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins
+// for debugging info. NB, This can kill the m'board and/or d'board if you
+// have anything except basic d'boards installed.
+
+// Uncomment the following to include optional circuitry
+
module usrp_sar
(output MYSTERY_SIGNAL,
input master_clk,
@@ -34,15 +40,14 @@
output FX2_2,
output FX2_3,
- // ADC bus
input wire [11:0] rx_a_a,
input wire [11:0] rx_b_a,
input wire [11:0] rx_a_b,
input wire [11:0] rx_b_b,
- // DAC bus
output wire [13:0] tx_a,
output wire [13:0] tx_b,
+
output wire TXSYNC_A,
output wire TXSYNC_B,
@@ -63,7 +68,7 @@
wire clk64;
- wire WR = usbctl[0]; // Not used
+ // wire WR = usbctl[0];
wire RD = usbctl[1];
wire OE = usbctl[2];
@@ -71,19 +76,14 @@
assign usbrdy[0] = 1'b0; // have_space;
assign usbrdy[1] = have_pkt_rdy;
- wire rx_overrun;
+ wire tx_underrun, rx_overrun;
wire clear_status = FX2_1;
assign FX2_2 = rx_overrun;
assign FX2_3 = 1'b0; // tx_underrun;
wire [15:0] usbdata_out;
-
- wire [3:0] rx_numchan;
- wire [2:0] tx_numchan;
-
- wire [7:0] interp_rate, decim_rate;
- wire [15:0] tx_debugbus, rx_debugbus;
+ wire [3:0] rx_numchan;
wire enable_tx, enable_rx;
wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
@@ -91,99 +91,88 @@
bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
assign clk64 = master_clk;
- wire strobe_interp, tx_sample_strobe;
- wire strobe_decim, rx_sample_strobe;
+
+ // TX
+ wire tx_sample_strobe;
wire tx_empty;
wire serial_strobe;
wire [6:0] serial_addr;
wire [31:0] serial_data;
-
- // Either one will reset both
- wire sar_reset = tx_dsp_reset|rx_dsp_reset;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit Side
-
+
wire [15:0] tx_i, tx_q;
- wire [15:0] tx_data;
- wire [15:0] tx_debug;
+ wire [15:0] tx_dac;
+
+ dac_interface dac(.clk_i(clk64),.rst_i(tx_dsp_reset),.ena_i(enable_tx),
+ .strobe_i(tx_sample_strobe),.tx_i_i(tx_i),.tx_q_i(tx_q),
+ .tx_data_o(tx_dac),.tx_sync_o(TXSYNC_A));
- wire sar_tx_strobe;
-`ifdef TX_RATE_MAX
- assign sar_tx_strobe = 1'b1;
-`else
- assign sar_tx_strobe = tx_sample_strobe; // Generated by
master_control, every other clock
-`endif
+ assign tx_a = tx_dac[15:2];
- // Transmitter creates a new output sample per sar_tx_strobe
- sar_tx
transmitter(.clk_i(clk64),.rst_i(sar_reset),.ena_i(enable_tx),.strobe_i(sar_tx_strobe),
-
.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
- .tx_i_o(tx_i),.tx_q_o(tx_q),.debug_o(tx_debug));
-
-
- dac_interface
dac_interface(.clk_i(clk64),.rst_i(sar_reset),.ena_i(enable_tx),.strobe_i(sar_tx_strobe),
-
.tx_i_i(tx_i),.tx_q_i(tx_q),.tx_data_o(tx_data),.tx_sync_o(TXSYNC_A));
-
- assign tx_a = tx_data[15:2];
- assign tx_b = 14'b0;
+ // Wedge DAC #2 at zero
assign TXSYNC_B = 1'b0;
+ assign tx_b = 14'b0;
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Receive Side
-
- wire [31:0] rssi_i,rssi_q;
- wire [15:0] rx_in_i,rx_in_q;
-
- adc_interface
adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
+ wire rx_sample_strobe, rx_strobe;
+ wire [15:0] rx_adc0_i, rx_adc0_q;
+ wire [15:0] rx_buf_i, rx_buf_q;
+
+ adc_interface
adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
-
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b),
-
.rssi_0(rssi_i),.rssi_1(rssi_q),.rssi_2(),.rssi_3(),
- .ddc0_in_i(rx_in_i),.ddc0_in_q(rx_in_q),
+
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(),.rx_b_b(),
+ .rssi_0(),.rssi_1(),.rssi_2(),.rssi_3(),
+ .ddc0_in_i(rx_adc0_i),.ddc0_in_q(rx_adc0_q),
.ddc1_in_i(),.ddc1_in_q(),
.ddc2_in_i(),.ddc2_in_q(),
-
.ddc3_in_i(),.ddc3_in_q(),.rx_numchan(rx_numchan));
+
.ddc3_in_i(),.ddc3_in_q(),.rx_numchan(rx_numchan) );
- wire [15:0] rx_i, rx_q;
- wire rx_strobe;
- wire [15:0] rx_debug;
-
- sar_rx
receiver(.clk_i(clk64),.rst_i(sar_reset),.ena_i(enable_rx),.strobe_i(rx_sample_strobe),
-
.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
- .cpi_i(decim_rate),.rx_in_i_i(rx_in_i),.rx_in_q_i(rx_in_q),
// we use decim_rate for convenience as CPI
-
.rx_i_o(rx_i),.rx_q_o(rx_q),.rx_strobe_o(rx_strobe),.debug_o(rx_debug));
-
-
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
- .ch_0(rx_i),.ch_1(rx_q),
+ .ch_0(rx_buf_i),.ch_1(rx_buf_q),
.ch_2(),.ch_3(),
.ch_4(),.ch_5(),
.ch_6(),.ch_7(),
- .rxclk(clk64),.rxstrobe(rx_strobe), // Note this is generated in bursts
from sar_rx
+ .rxclk(clk64),.rxstrobe(rx_strobe),
.clear_status(clear_status),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
- .debugbus());
+ .debugbus() );
+
+
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // Top level application
+ sar sar
+ (
.clk_i(clk64),.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
+
.tx_rst_i(tx_dsp_reset),.tx_enable_i(enable_tx),.tx_strobe_i(tx_sample_strobe),
+ .tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q),
+
.rx_rst_i(rx_dsp_reset),.rx_enable_i(enable_rx),.rx_strobe_i(rx_sample_strobe),.rx_strobe_o(rx_strobe),
+
.rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q),.rx_ech_i_o(rx_buf_i),.rx_ech_q_o(rx_buf_q)
+ );
+
+
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Control Functions
wire [31:0] capabilities;
- assign capabilities[7] = 1'b0; // `TX_CAP_HB;
- assign capabilities[6:4] = 3'd2; // `TX_CAP_NCHAN;
- assign capabilities[3] = 1'b0; // `RX_CAP_HB;
- assign capabilities[2:0] = 3'd2; // `RX_CAP_NCHAN;
+ assign capabilities[7] = 0; // `TX_CAP_HB;
+ assign capabilities[6:4] = 2; // `TX_CAP_NCHAN;
+ assign capabilities[3] = 0; // `RX_CAP_HB;
+ assign capabilities[2:0] = 2; // `RX_CAP_NCHAN;
serial_io serial_io
( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
.enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
-
.readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
- .readback_4(rssi_i),.readback_5(rssi_q),.readback_6(),.readback_7()
+ .readback_0(),.readback_1(),.readback_2(capabilities),.readback_3(),
+ .readback_4(),.readback_5(),.readback_6(),.readback_7()
);
wire [15:0] reg_0,reg_1,reg_2,reg_3;
@@ -193,12 +182,13 @@
.tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
- .interp_rate(interp_rate),.decim_rate(decim_rate),
- .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
- .rx_sample_strobe(rx_sample_strobe),.strobe_decim(), // Note we don't
use the strobe_decim output from here
+ .interp_rate(),.decim_rate(),
+ .tx_sample_strobe(tx_sample_strobe),.strobe_interp(),
+ .rx_sample_strobe(rx_sample_strobe),.strobe_decim(),
.tx_empty(tx_empty),
- .debug_0(),.debug_1(),.debug_2(tx_debug),.debug_3(rx_debug),
- .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3));
+ .debug_0(),.debug_1(),
+ .debug_2(),.debug_3(),
+ .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
io_pins io_pins
(.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/sar_tx.py
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/sar_tx.py
2007-05-05 20:50:56 UTC (rev 5247)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/sar_tx.py
2007-05-05 22:37:46 UTC (rev 5248)
@@ -6,24 +6,12 @@
from optparse import OptionParser
import math
-# Set to 0 for 32 MHz tx clock, 1 for 64 MHz tx clock
-# Must match config.vh in FPGA code
-TX_RATE_MAX = 0
-_tx_freq_divisor = 32e6*(TX_RATE_MAX+1)
+_tx_freq_divisor = 32e6
class sar_tx:
def __init__(self):
- if TX_RATE_MAX == 1:
- fname = 'usrp_sar_max.rbf'
- else:
- fname = 'usrp_sar.rbf'
- print "Using FPGA bitstream", fname
+ fname = 'usrp_sar.rbf'
self.trans = usrp.sink_s(fpga_filename=fname)
- if TX_RATE_MAX == 1:
- self.set_tx_intfc(0x09)
- self.set_tx_dig(0x11)
- self.set_tx_dll(0x49)
- self.set_tx_clkout(0x00)
self.set_amplitude(32000)
def set_amplitude(self, amplitude):
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Commit-gnuradio] r5248 - in gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src: fpga/lib fpga/rbf fpga/rbf/rev2 fpga/rbf/rev4 fpga/toplevel python,
jcorgan <=