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[Simulavr-devel] SPI addition
|
From: |
Keith Gudger |
|
Subject: |
[Simulavr-devel] SPI addition |
|
Date: |
Thu, 6 Nov 2003 16:08:33 -0800 (PST) |
Ted:
Attached is the patch to add SPI. I've checked it pretty thoroughly. If
you would like the additions to the 43320 files I sent you for checking
the timers out, I can send them to you.
I also attached spi.c and spi.h, which are needed for this patch to work.
PLEASE NOTE: While the diff was done to a cvs update I had just
completed, it doesn't work right with the current cvs - it needs the
interrupt patches for the SPI interrupt to fire (intvects.c and
intvects.h, plus avrcore changes).
This code will compile and work with the current version from cvs, you
just won't get the SPI interrupt. For code that is polling the SPIF bit,
it should still work (I checked it and it did for me). Also, the WCOL bit
works correctly.
Keith
? simulavr/devsupp.diff
? simulavr/src_old
? simulavr/src/config.h
? simulavr/src/sa_kg3.zip
Index: simulavr/src/devsupp.c
===================================================================
RCS file: /cvsroot/simulavr/simulavr/src/devsupp.c,v
retrieving revision 1.16
diff -u -r1.16 devsupp.c
--- simulavr/src/devsupp.c 21 Oct 2003 05:38:30 -0000 1.16
+++ simulavr/src/devsupp.c 6 Nov 2003 23:56:14 -0000
@@ -57,6 +57,7 @@
#include "eeprom.h"
#include "timers.h"
#include "ports.h"
+#include "spi.h"
#include "avrcore.h"
@@ -113,6 +114,7 @@
uint8_t acsr;
uint8_t wdtcr;
uint8_t timsk;
+ uint8_t spcr;
} mask;
};
@@ -142,7 +144,8 @@
/* mask.mcucr */ (mask_SE | mask_SM | mask_ISC01 | mask_ISC00),
/* mask.acsr */ (mask_ACD | mask_ACO | mask_ACI | mask_ACIE | mask_ACIS1
| mask_ACIS0),
/* mask.wdtcr */ (mask_WDE | mask_WDP2 | mask_WDP1 | mask_WDP0),
- /* mask.timsk */ (mask_TOIE0)
+ /* mask.timsk */ (mask_TOIE0),
+ /* mask.spcr */ 0
}
};
@@ -169,7 +172,8 @@
/* mask.acsr */ (mask_ACD | mask_ACO | mask_ACI | mask_ACIE |
mask_ACIC | mask_ACIS1 | mask_ACIS0),
/* mask.wdtcr */ (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 |
mask_WDP0),
- /* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_TICIE1 | mask_TOIE0)
+ /* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_TICIE1 | mask_TOIE0),
+ /* mask.spcr */ 0
}
};
@@ -196,7 +200,8 @@
/* mask.acsr */ (mask_ACD | mask_ACO | mask_ACI | mask_ACIE |
mask_ACIC | mask_ACIS1 | mask_ACIS0),
/* mask.wdtcr */ (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 |
mask_WDP0),
- /* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 |
mask_TOIE0)
+ /* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 |
mask_TOIE0),
+ /* mask.spcr */ (mask_SPIE)
}
};
@@ -223,7 +228,8 @@
/* mask.acsr */ (mask_ACD | mask_ACO | mask_ACI | mask_ACIE |
mask_ACIC | mask_ACIS1 | mask_ACIS0),
/* mask.wdtcr */ (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 |
mask_WDP0),
- /* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 |
mask_TOIE0)
+ /* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 |
mask_TOIE0),
+ /* mask.spcr */ (mask_SPIE)
}
};
@@ -249,7 +255,8 @@
/* mask.acsr */ (mask_ACD | mask_ACO | mask_ACI | mask_ACIE |
mask_ACIC | mask_ACIS1 | mask_ACIS0),
/* mask.wdtcr */ (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 |
mask_WDP0),
- /* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 |
mask_TOIE0)
+ /* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 |
mask_TOIE0),
+ /* mask.spcr */ (mask_SPIE)
}
};
@@ -276,7 +283,8 @@
/* mask.acsr */ (mask_ACD | mask_ACO | mask_ACI | mask_ACIE |
mask_ACIC | mask_ACIS1 | mask_ACIS0),
/* mask.wdtcr */ (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 |
mask_WDP0),
- /* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 |
mask_TOIE0)
+ /* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 |
mask_TOIE0),
+ /* mask.spcr */ (mask_SPIE)
}
};
@@ -303,7 +311,8 @@
/* mask.acsr */ (mask_ACD | mask_ACO | mask_ACI | mask_ACIE |
mask_ACIC | mask_ACIS1 | mask_ACIS0),
/* mask.wdtcr */ (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 |
mask_WDP0),
- /* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 |
mask_TOIE0)
+ /* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 |
mask_TOIE0),
+ /* mask.spcr */ (mask_SPIE)
}
};
@@ -330,7 +339,8 @@
/* mask.acsr */ (mask_ACD | mask_ACO | mask_ACI | mask_ACIE |
mask_ACIC | mask_ACIS1 | mask_ACIS0),
/* mask.wdtcr */ (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1 |
mask_WDP0),
- /* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 |
mask_TOIE0)
+ /* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1 |
mask_TOIE0),
+ /* mask.spcr */ (mask_SPIE)
}
};
@@ -357,7 +367,8 @@
/* mask.wdtcr */ (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1
| mask_WDP0),
/* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1
- | mask_TOIE0)
+ | mask_TOIE0),
+ /* mask.spcr */ (mask_SPIE)
}
};
@@ -384,7 +395,8 @@
/* mask.wdtcr */ (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1
| mask_WDP0),
/* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1
- | mask_TOIE0)
+ | mask_TOIE0),
+ /* mask.spcr */ 0
}
};
@@ -411,7 +423,8 @@
/* mask.wdtcr */ (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1
| mask_WDP0),
/* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1
- | mask_TOIE0)
+ | mask_TOIE0),
+ /* mask.spcr */ (mask_SPIE)
}
};
@@ -438,7 +451,8 @@
/* mask.wdtcr */ (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1
| mask_WDP0),
/* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1
- | mask_TOIE0)
+ | mask_TOIE0),
+ /* mask.spcr */ (mask_SPIE)
}
};
@@ -465,7 +479,8 @@
/* mask.wdtcr */ (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1
| mask_WDP0),
/* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1
- | mask_TOIE0)
+ | mask_TOIE0),
+ /* mask.spcr */ 0
}
};
@@ -492,7 +507,8 @@
/* mask.wdtcr */ (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1
| mask_WDP0),
/* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1
- | mask_TOIE0)
+ | mask_TOIE0),
+ /* mask.spcr */ (mask_SPIE)
}
};
@@ -519,7 +535,8 @@
/* mask.wdtcr */ (mask_WDTOE | mask_WDE | mask_WDP2 | mask_WDP1
| mask_WDP0),
/* mask.timsk */ (mask_TOIE1 | mask_OCIE1A | mask_OCIE1B | mask_TICIE1
- | mask_TOIE0)
+ | mask_TOIE0),
+ /* mask.spcr */ 0
}
};
@@ -644,6 +661,14 @@
if (dev->mask.timsk)
{
vdev = (VDevice *)timer_intr_new( dev->mask.timsk );
+ avr_core_attach_vdev( core, vdev );
+ }
+
+ if (dev->mask.spcr)
+ {
+ vdev = (VDevice *)spi_intr_new();
+ avr_core_attach_vdev( core, vdev );
+ vdev = (VDevice *)spi_new();
avr_core_attach_vdev( core, vdev );
}
/*
* $Id: spi.c,v 1.9 2003/11/04 22:22:34 kgudger Exp $
*
****************************************************************************
*
* simulavr - A simulator for the Atmel AVR family of microcontrollers.
* Copyright (C) 2001, 2002 Theodore A. Roth
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
****************************************************************************
*/
/**
* \file spi.c
* \brief Module to simulate the AVR's SPI module.
*
*/
#include <config.h>
#include <stdio.h>
#include <stdlib.h>
#include "avrerror.h"
#include "avrmalloc.h"
#include "avrclass.h"
#include "utils.h"
#include "callback.h"
#include "op_names.h"
#include "storage.h"
#include "flash.h"
#include "vdevs.h"
#include "memory.h"
#include "stack.h"
#include "register.h"
#include "sram.h"
#include "eeprom.h"
#include "timers.h"
#include "ports.h"
#include "spi.h"
#include "avrcore.h"
#include "intvects.h"
/******************************************************************************\
*
* SPI Interrupts
*
\******************************************************************************/
static uint8_t spi_intr_read ( VDevice *dev, int addr );
static void spi_intr_write ( VDevice *dev, int addr, uint8_t val );
static void spi_intr_reset ( VDevice *dev );
static char *spi_intr_reg_name ( VDevice *dev , int addr );
static int spi_intr_cb( uint64_t time, AvrClass *data ) ;
/** \brief Allocate a new SPI interrupt */
SPIIntr_T *spi_intr_new( void )
{
SPIIntr_T *spi;
spi = avr_new( SPIIntr_T, 1 );
spi_intr_construct( spi );
class_overload_destroy( (AvrClass *)spi, spi_intr_destroy );
return spi;
}
/** \brief Constructor for spi interrupt object. */
void spi_intr_construct( SPIIntr_T *spi )
{
char *name = "SPIIntr";
if (spi == NULL)
avr_error( "passed null ptr" );
vdev_construct( (VDevice *)spi, name, SPI_INTR_BASE, SPI_INTR_SIZE,
spi_intr_read, spi_intr_write, spi_intr_reset,
spi_intr_reg_name );
spi_intr_reset( (VDevice*)spi );
}
/** \brief Destructor for spi interrupt object. */
void spi_intr_destroy( void *spi )
{
if (spi == NULL)
return;
vdev_destroy( spi );
}
static uint8_t spi_intr_read( VDevice *dev, int addr )
{
SPIIntr_T *spi = (SPIIntr_T *)dev;
switch ( addr - vdev_get_base(dev) ) {
case SPI_INTR_SPCR_ADDR : return (spi->spcr );
case SPI_INTR_SPSR_ADDR :
if ( spi->spsr & mask_SPIF )
spi->spsr_read |= mask_SPIF ;
if ( spi->spsr & mask_WCOL )
spi->spsr_read |= mask_WCOL ;
return (spi->spsr );
default:
avr_error( "Bad address: 0x%04x", addr );
}
return 0; /* will never get here */
}
static void spi_intr_write( VDevice *dev, int addr, uint8_t val )
{
SPIIntr_T *spi = (SPIIntr_T *)dev;
CallBack *cb;
switch ( addr - vdev_get_base(dev) ) {
case SPI_INTR_SPCR_ADDR :
(spi->spcr = val);
if ( spi->spcr & mask_SPE )
{
/* we need to install the intr_cb function */
cb = callback_new( spi_intr_cb, (AvrClass *)spi );
spi->intr_cb = cb;
avr_core_async_cb_add( (AvrCore *)vdev_get_core(dev), cb );
}
else
{
spi->intr_cb = NULL; /* no interrupt are enabled, remove the
callback */
}
break;
default:
avr_error( "Bad address: 0x%04x", addr );
}
}
static void spi_intr_reset( VDevice *dev )
{
SPIIntr_T *spi = (SPIIntr_T *)dev;
spi->intr_cb = NULL;
spi->spcr = 0;
spi->spsr = 0;
spi->spsr_read = 0 ;
}
static char *spi_intr_reg_name( VDevice *dev , int addr )
{
switch ( addr - vdev_get_base(dev) ) {
case SPI_INTR_SPCR_ADDR : return ("SPCR" );
case SPI_INTR_SPSR_ADDR : return ("SPSR" );
default:
avr_error( "Bad address: 0x%04x", addr );
}
return NULL; /* will never get here */
}
static int spi_intr_cb( uint64_t time, AvrClass *data )
{
SPIIntr_T *spi = (SPIIntr_T *)data;
if ( spi->intr_cb == NULL )
return CB_RET_REMOVE;
if ( ( spi->spcr & mask_SPE ) && ( spi->spcr & mask_SPIE ) &&
( spi->spsr & mask_SPIF )) /* an enabled interrupt occured */
{
AvrCore *core = (AvrCore *)vdev_get_core((VDevice *)spi);
avr_core_irq_raise( core, irq_vect_table_index(SPI_STC) );
spi->spsr &= ~mask_SPIF;
spi->spsr = 0 ;
}
return CB_RET_RETAIN;
}
/******************************************************************************\
*
* SPI
*
\******************************************************************************/
static uint8_t spi_read ( VDevice *dev, int addr );
static void spi_write ( VDevice *dev, int addr, uint8_t val );
static void spi_reset ( VDevice *dev );
static char *spi_reg_name ( VDevice *dev , int addr );
static int spi_clk_incr_cb( uint64_t ck, AvrClass *data );
/** \brief Allocate a new SPI structure. */
SPI_T *spi_new( void )
{
SPI_T *spi;
spi = avr_new( SPI_T, 1 );
spi_construct( spi );
class_overload_destroy( (AvrClass *)spi, spi_destroy );
return spi;
}
/** \brief Constructor for SPI object. */
void spi_construct( SPI_T *spi )
{
char *name = "SPI";
if (spi == NULL)
avr_error( "passed null ptr" );
vdev_construct( (VDevice *)spi, name, SPI_BASE, SPI_SIZE,
spi_read, spi_write, spi_reset, spi_reg_name );
spi_reset( (VDevice*)spi );
}
/** \brief Destructor for SPI object. */
void spi_destroy( void *spi )
{
if (spi == NULL)
return;
vdev_destroy( spi );
}
static uint8_t spi_read( VDevice *dev, int addr )
{
SPI_T *spi = (SPI_T *)dev;
SPIIntr_T *spi_ti;
spi_ti = (SPIIntr_T *)avr_core_get_vdev_by_name( (AvrCore
*)vdev_get_core((VDevice *)spi),
"SPIIntr" );
switch ( addr - vdev_get_base(dev) ) {
case SPI_SPDR_ADDR:
if (spi_ti->spsr_read)
{
spi_ti->spsr &= ~ spi_ti->spsr_read ;
spi_ti->spsr_read = 0 ;
}
return spi->spdr;
default:
avr_error( "Bad address: 0x%04x", addr );
}
return 0; /* will never get here */
}
static void spi_write( VDevice *dev, int addr, uint8_t val )
{
SPI_T *spi = (SPI_T *)dev;
int offset = addr - vdev_get_base(dev);
CallBack *cb;
SPIIntr_T *spi_ti;
spi_ti = (SPIIntr_T *)avr_core_get_vdev_by_name( (AvrCore
*)vdev_get_core((VDevice *)spi),
"SPIIntr" );
if ( offset == SPI_SPDR_ADDR )
{
if (spi_ti->spsr_read)
{
spi_ti->spsr &= ~ spi_ti->spsr_read ;
spi_ti->spsr_read = 0 ;
}
if ( spi->tcnt != 0 )
{
spi_ti->spsr |= mask_WCOL ;
}
spi->spdr = val;
/*
* When the user writes to SPDR, a callback is installed for either
* clock generated increments or externally generated increments. The
* two incrememtor callback are mutally exclusive, only one or the
* other can be installed at any given instant.
*/
switch ( (spi_ti->spcr) & (mask_SPR0 | mask_SPR1) ) {
case SPI_CK_4:
spi->divisor = 4;
break;
case SPI_CK_16:
spi->divisor = 16;
break;
case SPI_CK_64:
spi->divisor = 64;
break;
case SPI_CK_128:
spi->divisor = 128;
break;
default:
avr_error( "The impossible happened!" );
}
/* install the clock incrementor callback (with flair!) */
if (spi->clk_cb == NULL)
{
cb = callback_new( spi_clk_incr_cb, (AvrClass *)spi );
spi->clk_cb = cb;
avr_core_clk_cb_add( (AvrCore *)vdev_get_core((VDevice *)spi), cb );
}
spi->tcnt = 8 ; /* set up timer for 8 clocks */
spi->spdr_in = spi_port_rd( addr ) ;
}
else
{
avr_error( "Bad address: 0x%04x", addr );
}
}
static void spi_reset( VDevice *dev )
{
SPI_T *spi = (SPI_T *)dev;
spi->clk_cb = NULL;
spi->spdr = 0;
spi->tcnt = 0;
spi->divisor = 0;
}
static char *spi_reg_name( VDevice *dev , int addr )
{
switch ( addr - vdev_get_base(dev) ) {
case SPI_SPDR_ADDR: return "SPDR";
default:
avr_error( "Bad address: 0x%04x", addr );
}
return NULL;
}
static int spi_clk_incr_cb( uint64_t ck, AvrClass *data )
{
SPI_T *spi = (SPI_T *)data;
uint8_t last = spi->tcnt;
SPIIntr_T *spi_ti;
spi_ti = (SPIIntr_T *)avr_core_get_vdev_by_name( (AvrCore
*)vdev_get_core((VDevice *)spi),
"SPIIntr" );
if (spi->clk_cb == NULL)
return CB_RET_REMOVE;
if (spi->divisor <= 0)
avr_error( "Bad divisor value: %d", spi->divisor );
/* decrement clock if ck is a mutliple of divisor */
spi->tcnt -= ((ck % spi->divisor) == 0);
/* */
if (spi->tcnt != last) /* we've changed the counter */
{
if ( spi->tcnt == 0 )
{
spi_ti->spsr |= mask_SPIF; /* spdr is not guaranteed until
operation complete */
spi_port_wr(spi->spdr) ; /* tell what we wrote */
spi->spdr = spi->spdr_in ; /* update spdr to what we read */
return CB_RET_REMOVE;
}
}
return CB_RET_RETAIN;
}
uint8_t spi_port_rd( int addr )
{
int data;
char line[80];
while (1)
{
fprintf( stderr, "\nEnter a byte of hex data to read into the SPI at
address 0x%04x: ",
addr);
/* try to read in a line of input */
if ( fgets(line, sizeof(line), stdin) == NULL)
continue;
/* try to parse the line for a byte of data */
if ( sscanf(line, "%x\n", &data) != 1 )
continue;
break;
}
return (uint8_t)(data & 0xff);
}
void spi_port_wr( uint8_t val )
{
fprintf( stderr, "wrote 0x%02x to SPI\n", val );
}
/*
* $Id: spi.h,v 1.3 2003/11/04 20:58:28 kgudger Exp $
*
****************************************************************************
*
* simulavr - A simulator for the Atmel AVR family of microcontrollers.
* Copyright (C) 2001, 2002 Theodore A. Roth
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
****************************************************************************
*/
#ifndef SPI_H
#define SPI_H
/****************************************************************************\
*
* SPIInter_T(VDevice) : SPI Interrupt and Control Register
*
\****************************************************************************/
enum _spi_intr_constants {
SPI_INTR_BASE = 0x2d, /* base address for vdev */
SPI_INTR_SIZE = 2, /* SPCR, SPSR */
SPI_INTR_SPCR_ADDR = 0,
SPI_INTR_SPSR_ADDR = 1,
};
typedef enum {
bit_SPR0 = 0, /* Clock Rate Select 0 */
bit_SPR1 = 1, /* Clock Rate Select 1 */
bit_CPHA = 2, /* Clock Phase */
bit_CPOL = 3, /* Clock Polarity */
bit_MSTR = 4, /* Master / Slave Select */
bit_DORD = 5, /* Data Order */
bit_SPE = 6, /* SPI Enable */
bit_SPIE = 7, /* SPI Interrupt Enable */
} SPCR_BITS;
typedef enum {
mask_SPR0 = 1 << bit_SPR0,
mask_SPR1 = 1 << bit_SPR1,
mask_SPE = 1 << bit_SPE,
mask_SPIE = 1 << bit_SPIE,
} SPCR_MASKS;
typedef enum {
bit_WCOL = 6, /* Write Collision flag */
bit_SPIF = 7, /* SPI Interrupt flag */
} SPSR_BITS;
typedef enum {
mask_WCOL = 1 << bit_WCOL,
mask_SPIF = 1 << bit_SPIF,
} SPSR_MASKS;
typedef struct _SPIIntr_T SPIIntr_T;
struct _SPIIntr_T {
VDevice parent;
uint8_t spcr; /* SPI Interrupt and control mask register */
uint8_t spsr; /* SPI Interrupt and Write Coll flag register */
uint8_t spsr_read; /* SPCR read occured with SPIF set */
CallBack *intr_cb; /* callback for checking and raising interrupts
*/
};
extern SPIIntr_T *spi_intr_new ( void );
extern void spi_intr_construct ( SPIIntr_T *ti );
extern void spi_intr_destroy ( void *ti );
/****************************************************************************\
*
* General SPI bits and masks.
*
\****************************************************************************/
enum _spi_cs_constants {
SPI_CK_4 = 0x00, /* CK/4 */
SPI_CK_16 = 0x01, /* CK/16 */
SPI_CK_64 = 0x02, /* CK/64 */
SPI_CK_128 = 0x03, /* CK/128 */
};
/****************************************************************************\
*
* SPI(VDevice) : SPI
*
\****************************************************************************/
enum _spi_constants {
SPI_BASE = 0x2f, /* base memory address */
SPI_SIZE = 1, /* SPDR */
SPI_SPDR_ADDR = 0, /* offset from base to SPDR Register */
};
typedef struct _SPI SPI_T;
struct _SPI {
VDevice parent;
uint8_t spdr; /* data register */
uint8_t spdr_in; /* new data register */
uint8_t tcnt; /* SPI timer up-counter register */
uint8_t divisor; /* clock divisor */
CallBack *clk_cb; /* incr timer tied to clock */
};
extern SPI_T *spi_new ( void );
extern void spi_construct ( SPI_T *spi );
extern void spi_destroy ( void *spi );
extern void spi_intr_set_flag ( SPIIntr_T *ti );
extern void spi_intr_clear_flag ( SPIIntr_T *ti );
extern uint8_t spi_port_rd( int addr ) ;
extern void spi_port_wr( uint8_t val );
#endif
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Keith Gudger <=