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[Qemu-riscv] [RFC v1 04/23] target/riscv: Add the force HS exception mod
From: |
Alistair Francis |
Subject: |
[Qemu-riscv] [RFC v1 04/23] target/riscv: Add the force HS exception mode |
Date: |
Fri, 24 May 2019 16:45:45 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_bits.h | 6 ++++++
target/riscv/cpu_helper.c | 23 +++++++++++++++++++++++
3 files changed, 31 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index de4843b879..eeb3756c91 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -282,6 +282,8 @@ int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t
*buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
+bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
+void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 07c95e8d2c..c898bb1102 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -423,6 +423,12 @@
#define VIRT_MODE_SHIFT 0
#define VIRT_MODE_MASK (1 << VIRT_MODE_SHIFT)
+/* HS-level exceptions modes */
+#define CLEAR_HS_EXCEP 0
+#define FORCE_HS_EXCEP 1
+#define FORCE_HS_EXCEP_SHIFT 1
+#define FORCE_HS_EXCEP_MASK (1 << FORCE_HS_EXCEP_SHIFT)
+
/* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000
#define SATP32_ASID 0x7fc00000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 5912ae63b7..0fdc81f71f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -94,6 +94,29 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool
enable)
env->virt |= enable << VIRT_MODE_SHIFT;
}
+bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env)
+{
+ bool tmp;
+
+ if (!riscv_has_ext(env, RVH)) {
+ return false;
+ }
+
+ tmp = (env->virt & FORCE_HS_EXCEP_MASK) >> FORCE_HS_EXCEP_SHIFT;
+
+ return tmp == FORCE_HS_EXCEP;
+}
+
+void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return;
+ }
+
+ env->virt &= ~FORCE_HS_EXCEP_MASK;
+ env->virt |= enable << FORCE_HS_EXCEP_SHIFT;
+}
+
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{
CPURISCVState *env = &cpu->env;
--
2.21.0
- [Qemu-riscv] [RFC v1 19/23] target/riscv: Allow specifying MMU stage, (continued)
- [Qemu-riscv] [RFC v1 19/23] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 18/23] target/riscv: Add hfence instructions, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 17/23] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 15/23] riscv: plic: Always set sip.SEIP bit for HS, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 14/23] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 13/23] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 16/23] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 10/23] target/riscv: Add background CSRs accesses, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 09/23] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 08/23] target/riscv: Add support for background interrupt setting, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 04/23] target/riscv: Add the force HS exception mode,
Alistair Francis <=
- [Qemu-riscv] [RFC v1 12/23] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 11/23] target/riscv: Add background register swapping function, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 06/23] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 01/23] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 07/23] target/riscv: Remove strict perm checking for CSR R/W, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 03/23] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 05/23] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 02/23] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/05/24