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[Qemu-riscv] [RFC v1 05/23] target/riscv: Add the Hypervisor CSRs to CPU
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [RFC v1 05/23] target/riscv: Add the Hypervisor CSRs to CPUState |
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Date: |
Fri, 24 May 2019 16:45:48 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index eeb3756c91..b99d2b7af2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -169,12 +169,29 @@ struct CPURISCVState {
target_ulong mcause;
target_ulong mtval; /* since: priv-1.10.0 */
+ /* Hypervisor CSRs */
+ target_ulong hstatus;
+ target_ulong hedeleg;
+ target_ulong hideleg;
+ target_ulong hgatp;
+
target_ulong scounteren;
target_ulong mcounteren;
target_ulong sscratch;
target_ulong mscratch;
+ /* Background CSRs */
+ target_ulong bsstatus;
+ target_ulong bsip;
+ target_ulong bsie;
+ target_ulong bstvec;
+ target_ulong bsscratch;
+ target_ulong bsepc;
+ target_ulong bscause;
+ target_ulong bstval;
+ target_ulong bsatp;
+
/* temporary htif regs */
uint64_t mfromhost;
uint64_t mtohost;
--
2.21.0
- [Qemu-riscv] [RFC v1 10/23] target/riscv: Add background CSRs accesses, (continued)
- [Qemu-riscv] [RFC v1 10/23] target/riscv: Add background CSRs accesses, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 09/23] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 08/23] target/riscv: Add support for background interrupt setting, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 04/23] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 12/23] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 11/23] target/riscv: Add background register swapping function, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 06/23] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 01/23] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 07/23] target/riscv: Remove strict perm checking for CSR R/W, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 03/23] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 05/23] target/riscv: Add the Hypervisor CSRs to CPUState,
Alistair Francis <=
- [Qemu-riscv] [RFC v1 02/23] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/05/24