[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-riscv] [RFC v1 14/23] riscv: tcg-target: Add the out load and stor
From: |
Alistair Francis |
Subject: |
[Qemu-riscv] [RFC v1 14/23] riscv: tcg-target: Add the out load and store instructions |
Date: |
Thu, 15 Nov 2018 22:36:00 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
---
tcg/riscv/tcg-target.inc.c | 56 ++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 646a4d3ebd..bc433170c4 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -518,6 +518,62 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret,
TCGReg arg)
tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
}
+static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
+ TCGReg addr, intptr_t offset)
+{
+ int32_t imm12 = sextract32(offset, 0, 12);
+ if (offset != imm12) {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12);
+ if (addr != TCG_REG_ZERO) {
+ tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr);
+ }
+ addr = TCG_REG_TMP2;
+ }
+ switch (opc) {
+ case OPC_SB:
+ case OPC_SH:
+ case OPC_SW:
+ case OPC_SD:
+ tcg_out_opc_store(s, opc, addr, data, imm12);
+ break;
+ case OPC_LB:
+ case OPC_LBU:
+ case OPC_LH:
+ case OPC_LHU:
+ case OPC_LW:
+ case OPC_LWU:
+ case OPC_LD:
+ tcg_out_opc_imm(s, opc, data, addr, imm12);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
+{
+ bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
+ tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2);
+}
+
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
+{
+ bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
+ tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2);
+}
+
+static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+ TCGReg base, intptr_t ofs)
+{
+ if (val == 0) {
+ tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
+ return true;
+ }
+ return false;
+}
+
void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
uintptr_t addr)
{
--
2.19.1
- Re: [Qemu-riscv] [Qemu-devel] [RFC v1 11/23] riscv: tcg-target: Add the relocation functions, (continued)
[Qemu-riscv] [RFC v1 10/23] riscv: tcg-target: Add the instruction emitters, Alistair Francis, 2018/11/15
[Qemu-riscv] [RFC v1 12/23] riscv: tcg-target: Add the mov and movi instruction, Alistair Francis, 2018/11/15
[Qemu-riscv] [RFC v1 13/23] riscv: tcg-target: Add the extract instructions, Alistair Francis, 2018/11/15
[Qemu-riscv] [RFC v1 14/23] riscv: tcg-target: Add the out load and store instructions,
Alistair Francis <=
[Qemu-riscv] [RFC v1 15/23] riscv: tcg-target: Add branch and jump instructions, Alistair Francis, 2018/11/15
[Qemu-riscv] [RFC v1 16/23] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/11/15