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[Qemu-ppc] [PATCH v1 09/10] target-ppc: improve stxvw4x implementation
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH v1 09/10] target-ppc: improve stxvw4x implementation |
Date: |
Thu, 11 Aug 2016 00:31:05 +0530 |
Manipulate data and store 8bytes instead of 4bytes.
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/translate/vsx-impl.inc.c | 27 +++++++++++++--------------
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/target-ppc/translate/vsx-impl.inc.c
b/target-ppc/translate/vsx-impl.inc.c
index 8912fe9..498b6ea 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -204,7 +204,8 @@ static void gen_stxvd2x(DisasContext *ctx)
static void gen_stxvw4x(DisasContext *ctx)
{
- TCGv_i64 tmp;
+ TCGv_i64 xsh = cpu_vsrh(xS(ctx->opcode));
+ TCGv_i64 xsl = cpu_vsrl(xS(ctx->opcode));
TCGv EA;
if (unlikely(!ctx->vsx_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VSXU);
@@ -213,21 +214,19 @@ static void gen_stxvw4x(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_INT);
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
- tmp = tcg_temp_new_i64();
-
- tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
- gen_qemu_st32_i64(ctx, tmp, EA);
- tcg_gen_addi_tl(EA, EA, 4);
- gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
-
- tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
- tcg_gen_addi_tl(EA, EA, 4);
- gen_qemu_st32_i64(ctx, tmp, EA);
- tcg_gen_addi_tl(EA, EA, 4);
- gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
+ if (ctx->le_mode) {
+ tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ);
+ tcg_gen_addi_tl(EA, EA, 8);
+ tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ);
+ } else {
+ gen_helper_bswap32x2(xsh, xsh);
+ tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_LEQ);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_helper_bswap32x2(xsl, xsl);
+ tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_LEQ);
+ }
tcg_temp_free(EA);
- tcg_temp_free_i64(tmp);
}
#define MV_VSRW(name, tcgop1, tcgop2, target, source) \
--
2.7.4
- Re: [Qemu-ppc] [PATCH v1 02/10] target-ppc: consolidate load operations, (continued)
[Qemu-ppc] [PATCH v1 03/10] target-ppc: consolidate store operations, Nikunj A Dadhania, 2016/08/10
[Qemu-ppc] [PATCH v1 06/10] target-ppc: add stxsi[bh]x instruction, Nikunj A Dadhania, 2016/08/10
[Qemu-ppc] [PATCH v1 05/10] target-ppc: add lxsi[bw]zx instruction, Nikunj A Dadhania, 2016/08/10
[Qemu-ppc] [PATCH v1 04/10] target-ppc: Implement darn instruction, Nikunj A Dadhania, 2016/08/10
[Qemu-ppc] [PATCH v1 07/10] target-ppc: improve lxvw4x implementation, Nikunj A Dadhania, 2016/08/10
[Qemu-ppc] [PATCH v1 10/10] target-ppc: add stxvb16x and stxvh8x, Nikunj A Dadhania, 2016/08/10
[Qemu-ppc] [PATCH v1 08/10] target-ppc: add lxvb16x and lxvh8x, Nikunj A Dadhania, 2016/08/10
[Qemu-ppc] [PATCH v1 09/10] target-ppc: improve stxvw4x implementation,
Nikunj A Dadhania <=