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[Qemu-ppc] [PATCH v1 06/10] target-ppc: add stxsi[bh]x instruction
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH v1 06/10] target-ppc: add stxsi[bh]x instruction |
Date: |
Thu, 11 Aug 2016 00:31:02 +0530 |
stxsibx - Store VSX Scalar as Integer Byte Indexed
stxsihx - Store VSX Scalar as Integer Halfword Indexed
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/translate.c | 2 ++
target-ppc/translate/vsx-impl.inc.c | 2 ++
target-ppc/translate/vsx-ops.inc.c | 2 ++
3 files changed, 6 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1fc78d9..efa5fd1 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2536,6 +2536,8 @@ static void glue(gen_qemu_, glue(stop,
_i64))(DisasContext *ctx, \
op | ctx->default_tcg_memop_mask); \
}
+GEN_QEMU_STORE_64(st8, MO_UB)
+GEN_QEMU_STORE_64(st16, MO_UW)
GEN_QEMU_STORE_64(st32, MO_UL)
static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
diff --git a/target-ppc/translate/vsx-impl.inc.c
b/target-ppc/translate/vsx-impl.inc.c
index 9cb48e1..70812cb 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -118,6 +118,8 @@ static void gen_##name(DisasContext *ctx)
\
}
VSX_STORE_SCALAR(stxsdx, st64)
+VSX_STORE_SCALAR(stxsibx, st8_i64)
+VSX_STORE_SCALAR(stxsihx, st16_i64)
VSX_STORE_SCALAR(stxsiwx, st32_i64)
VSX_STORE_SCALAR(stxsspx, st32fs)
diff --git a/target-ppc/translate/vsx-ops.inc.c
b/target-ppc/translate/vsx-ops.inc.c
index 4f32837..d7be8ee 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -9,6 +9,8 @@ GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(stxsibx, 0x1F, 0xD, 0x1C, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stxsihx, 0x1F, 0xD, 0x1D, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
--
2.7.4
[Qemu-ppc] [PATCH v1 03/10] target-ppc: consolidate store operations, Nikunj A Dadhania, 2016/08/10
[Qemu-ppc] [PATCH v1 06/10] target-ppc: add stxsi[bh]x instruction,
Nikunj A Dadhania <=
[Qemu-ppc] [PATCH v1 05/10] target-ppc: add lxsi[bw]zx instruction, Nikunj A Dadhania, 2016/08/10
[Qemu-ppc] [PATCH v1 04/10] target-ppc: Implement darn instruction, Nikunj A Dadhania, 2016/08/10
[Qemu-ppc] [PATCH v1 07/10] target-ppc: improve lxvw4x implementation, Nikunj A Dadhania, 2016/08/10
[Qemu-ppc] [PATCH v1 10/10] target-ppc: add stxvb16x and stxvh8x, Nikunj A Dadhania, 2016/08/10
[Qemu-ppc] [PATCH v1 08/10] target-ppc: add lxvb16x and lxvh8x, Nikunj A Dadhania, 2016/08/10
[Qemu-ppc] [PATCH v1 09/10] target-ppc: improve stxvw4x implementation, Nikunj A Dadhania, 2016/08/10