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[Qemu-ppc] [PATCH v2 02/10] ppc: define a default LPCR value
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH v2 02/10] ppc: define a default LPCR value |
Date: |
Tue, 21 Jun 2016 23:48:47 +0200 |
From: Benjamin Herrenschmidt <address@hidden>
This allows us to set the appropriate LPCR bits which will be used
when fixing the exception model for the HV mode.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[clg: previous commit 26a7f1291bb5 did not include the LPCR setting as
it was not needed at the time, adapted commit log ]
Signed-off-by: Cédric Le Goater <address@hidden>
---
target-ppc/translate_init.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index ca894ff4af45..edfd91a85425 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8509,6 +8509,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
void cpu_ppc_set_papr(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
+ ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
ppc_spr_t *amor = &env->spr_cb[SPR_AMOR];
/* PAPR always has exception vectors in RAM not ROM. To ensure this,
@@ -8518,6 +8519,19 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu)
*/
env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
+ /* Set emulated LPCR to not send interrupts to hypervisor. Note that
+ * under KVM, the actual HW LPCR will be set differently by KVM itself,
+ * the settings below ensure proper operations with TCG in absence of
+ * a real hypervisor
+ */
+ lpcr->default_value &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV);
+ lpcr->default_value |= LPCR_LPES0 | LPCR_LPES1;
+
+ /* We should be followed by a CPU reset but update the active value
+ * just in case...
+ */
+ env->spr[SPR_LPCR] = lpcr->default_value;
+
/* Set a full AMOR so guest can use the AMR as it sees fit */
env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull;
--
2.1.4
[Qemu-ppc] [PATCH v2 02/10] ppc: define a default LPCR value,
Cédric Le Goater <=
[Qemu-ppc] [PATCH v2 03/10] ppc: fix exception model for HV mode, Cédric Le Goater, 2016/06/21
[Qemu-ppc] [PATCH v2 04/10] ppc: Fix POWER7 and POWER8 exception definitions, Cédric Le Goater, 2016/06/21
[Qemu-ppc] [PATCH v2 05/10] ppc: Fix generation if ISI/DSI vs. HV mode, Cédric Le Goater, 2016/06/21
[Qemu-ppc] [PATCH v2 06/10] ppc: Rework generation of priv and inval interrupts, Cédric Le Goater, 2016/06/21
[Qemu-ppc] [PATCH v2 07/10] ppc: Add real mode CI load/store instructions for P7 and P8, Cédric Le Goater, 2016/06/21
[Qemu-ppc] [PATCH v2 08/10] ppc: Turn a bunch of booleans from int to bool, Cédric Le Goater, 2016/06/21
[Qemu-ppc] [PATCH v2 09/10] ppc: Move exception generation code out of line, Cédric Le Goater, 2016/06/21