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Re: [Qemu-devel] [PATCH v3] target/mips: Fix minor bug in FPU


From: Mateja Marjanovic
Subject: Re: [Qemu-devel] [PATCH v3] target/mips: Fix minor bug in FPU
Date: Wed, 20 Mar 2019 12:22:15 +0100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1


On 19.3.19. 23:02, Alex Bennée wrote:
Aleksandar Markovic <address@hidden> writes:

From: Peter Maydell <address@hidden>
Subject: Re: [PATCH v3] target/mips: Fix minor bug in FPU

On Tue, 19 Mar 2019 at 19:21, Aleksandar Markovic
<address@hidden> wrote:
From: Mateja Marjanovic <address@hidden>
Subject: [PATCH v3] target/mips: Fix minor bug in FPU

From: Mateja Marjanovic <address@hidden>

Wrong type of NaN was generated for IEEE 754-2008 by MADDF.<D|S> and
MSUBF.<D|S> instructions when the arguments were (inf, zero, nan) or
(zero, inf, nan).
These instructions were tested and the results match with the results
of the machine that has a MIPS64 r6 cpu.

Signed-off-by: Mateja Marjanovic <address@hidden>
---
Mateja,

The commit message is missing information on the reference source
of information, that you placed in the cover letter. In my opinion, this is
an important peace of information for anybody seeing and examining
this patch in future, so please submit a new version of the patch as an
isolated patch and updated commit message.
If Alex is willing to edit the commit message in his tree
that would save Mateja from having to do another respin.

Sure, that would be a good option. Whoever (Alex or Mateja) modifies
the patch, the commit message should please read: (I did some
rearranging and editing)


Wrong type of NaN was generated for IEEE 754-2008 by MADDF.<D|S> and
MSUBF.<D|S> instructions when the arguments were (Inf, Zero, NaN) or
(Zero, Inf, NaN).

The if-else statement establishes if the system conforms to IEEE
754-1985 or IEEE 754-2008, and defines different behaviors depending
on that. In case of IEEE 754-2008, in mentioned cases of inputs,
<MADDF|MSUBF>.<D|S> returns the input value 'c' [2] (page 53) and
raises floating point exception 'Invalid Operation' [1] (pages 349,
350).

These scenarios were tested and the results in QEMU emulation match
the results obtained on the machine that has a MIPS64R6 CPU.

[1] MIPS Architecture for Programmers Volume II-a: The MIPS64
     Instruction Set Reference Manual, Revision 6.06
[2] MIPS Architecture for Programmers Volume IV-j: The MIPS64
     SIMD Architecture Module, Revision 1.12

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Mateja Marjanovic <address@hidden>
I've updated the commit message, thanks.
I really appreciate this.
--
Alex Bennée
Regards,

Mateja




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