[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 29/47] target/arm/translate-a64: Don't underdecode ad
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 29/47] target/arm/translate-a64: Don't underdecode add/sub extended register |
Date: |
Fri, 1 Feb 2019 16:06:35 +0000 |
In the "add/subtract (extended register)" encoding group, the "opt"
field in bits [23:22] must be zero. Correctly UNDEF the unallocated
encodings where this field is not zero.
Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden
---
target/arm/translate-a64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2cade64ed25..94907f0ae97 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -4201,6 +4201,7 @@ static void disas_add_sub_ext_reg(DisasContext *s,
uint32_t insn)
int imm3 = extract32(insn, 10, 3);
int option = extract32(insn, 13, 3);
int rm = extract32(insn, 16, 5);
+ int opt = extract32(insn, 22, 2);
bool setflags = extract32(insn, 29, 1);
bool sub_op = extract32(insn, 30, 1);
bool sf = extract32(insn, 31, 1);
@@ -4209,7 +4210,7 @@ static void disas_add_sub_ext_reg(DisasContext *s,
uint32_t insn)
TCGv_i64 tcg_rd;
TCGv_i64 tcg_result;
- if (imm3 > 4) {
+ if (imm3 > 4 || opt != 0) {
unallocated_encoding(s);
return;
}
--
2.20.1
- [Qemu-devel] [PULL 00/47] target-arm queue, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 02/47] armv7m: Don't assume the NVIC's CPU is CPU 0, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 01/47] hw/arm/nrf51_soc: set object owner in memory_region_init_ram, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 03/47] armv7m: Make cpu object a child of the armv7m container, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 04/47] armv7m: Pass through start-powered-off CPU property, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 18/47] hw/arm/armsse: Add unimplemented-device stub for cache control registers, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 05/47] hw/arm/iotkit: Rename IoTKit to ARMSSE, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 14/47] hw/arm/armsse: Put each CPU in its own cluster object, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 06/47] hw/arm/iotkit: Refactor into abstract base class and subclass, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 29/47] target/arm/translate-a64: Don't underdecode add/sub extended register,
Peter Maydell <=
- [Qemu-devel] [PULL 22/47] hw/arm/armsse: Add SSE-200 model, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 07/47] hw/arm/iotkit: Rename 'iotkit' local variables and functions, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 21/47] hw/arm/armsse: Add CPU_IDENTITY block to SSE-200, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 42/47] linux-user: Initialize aarch64 pac keys, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 31/47] target/arm/translate-a64: Don't underdecode SDOT and UDOT, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 27/47] target/arm/translate-a64: Don't underdecode SIMD ld/st multiple, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 35/47] target/arm: Send interrupts on PMU counter overflow, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 25/47] target/arm/translate-a64: Don't underdecode system instructions, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 40/47] aarch64-linux-user: Update HWCAP bits from linux 5.0-rc1, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 30/47] target/arm/translate-a64: Don't underdecode FP insns, Peter Maydell, 2019/02/01