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[Qemu-devel] [PULL 29/42] tcg: Add reachable_code_pass
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 29/42] tcg: Add reachable_code_pass |
Date: |
Wed, 26 Dec 2018 07:55:16 +1100 |
Delete trivially dead code that follows unconditional branches and
noreturn helpers. These can occur either via optimization or via
the structure of a target's translator following an exception.
Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/tcg.c | 76 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 99afc65126..d2be550ab4 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2239,6 +2239,81 @@ TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op,
TCGOpcode opc)
return new_op;
}
+/* Reachable analysis : remove unreachable code. */
+static void reachable_code_pass(TCGContext *s)
+{
+ TCGOp *op, *op_next;
+ bool dead = false;
+
+ QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
+ bool remove = dead;
+ TCGLabel *label;
+ int call_flags;
+
+ switch (op->opc) {
+ case INDEX_op_set_label:
+ label = arg_label(op->args[0]);
+ if (label->refs == 0) {
+ /*
+ * While there is an occasional backward branch, virtually
+ * all branches generated by the translators are forward.
+ * Which means that generally we will have already removed
+ * all references to the label that will be, and there is
+ * little to be gained by iterating.
+ */
+ remove = true;
+ } else {
+ /* Once we see a label, insns become live again. */
+ dead = false;
+ remove = false;
+
+ /*
+ * Optimization can fold conditional branches to unconditional.
+ * If we find a label with one reference which is preceded by
+ * an unconditional branch to it, remove both. This needed to
+ * wait until the dead code in between them was removed.
+ */
+ if (label->refs == 1) {
+ TCGOp *op_prev = QTAILQ_PREV(op, TCGOpHead, link);
+ if (op_prev->opc == INDEX_op_br &&
+ label == arg_label(op_prev->args[0])) {
+ tcg_op_remove(s, op_prev);
+ remove = true;
+ }
+ }
+ }
+ break;
+
+ case INDEX_op_br:
+ case INDEX_op_exit_tb:
+ case INDEX_op_goto_ptr:
+ /* Unconditional branches; everything following is dead. */
+ dead = true;
+ break;
+
+ case INDEX_op_call:
+ /* Notice noreturn helper calls, raising exceptions. */
+ call_flags = op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op) + 1];
+ if (call_flags & TCG_CALL_NO_RETURN) {
+ dead = true;
+ }
+ break;
+
+ case INDEX_op_insn_start:
+ /* Never remove -- we need to keep these for unwind. */
+ remove = false;
+ break;
+
+ default:
+ break;
+ }
+
+ if (remove) {
+ tcg_op_remove(s, op);
+ }
+ }
+}
+
#define TS_DEAD 1
#define TS_MEM 2
@@ -3515,6 +3590,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
atomic_set(&prof->la_time, prof->la_time - profile_getclock());
#endif
+ reachable_code_pass(s);
liveness_pass_1(s);
if (s->nb_indirects > 0) {
--
2.17.2
- [Qemu-devel] [PULL 19/42] tcg/riscv: Add the prologue generation and register the JIT, (continued)
- [Qemu-devel] [PULL 19/42] tcg/riscv: Add the prologue generation and register the JIT, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 20/42] tcg/riscv: Add the target init code, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 21/42] tcg: Add RISC-V cpu signal handler, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 22/42] disas: Add RISC-V support, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 23/42] configure: Add support for building RISC-V host, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 24/42] disas/microblaze: Remove unused REG_SP macro, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 25/42] linux-user: Add safe_syscall for riscv64 host, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 26/42] tcg: Renumber TCG_CALL_* flags, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 27/42] tcg: Add TCG_CALL_NO_RETURN, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 28/42] tcg: Reference count labels, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 29/42] tcg: Add reachable_code_pass,
Richard Henderson <=
- [Qemu-devel] [PULL 30/42] tcg: Add preferred_reg argument to tcg_reg_alloc, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 31/42] tcg: Add preferred_reg argument to temp_load, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 32/42] tcg: Add preferred_reg argument to temp_sync, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 33/42] tcg: Add preferred_reg argument to tcg_reg_alloc_do_movi, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 34/42] tcg: Add output_pref to TCGOp, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 35/42] tcg: Improve register allocation for matching constraints, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 36/42] tcg: Dump register preference info with liveness, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 37/42] tcg: Reindent parts of liveness_pass_1, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 38/42] tcg: Rename and adjust liveness_pass_1 helpers, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 39/42] tcg: Split out more subroutines from liveness_pass_1, Richard Henderson, 2018/12/25