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[Qemu-devel] [PULL 24/42] disas/microblaze: Remove unused REG_SP macro
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 24/42] disas/microblaze: Remove unused REG_SP macro |
Date: |
Wed, 26 Dec 2018 07:55:11 +1100 |
This causes a build error with debian sid, riscv64 host:
disas/microblaze.c:179: error: "REG_SP" redefined [-Werror]
#define REG_SP 1 /* stack pointer */
In file included from /usr/include/signal.h:306,
from include/qemu/osdep.h:101,
from disas/microblaze.c:36:
/usr/include/riscv64-linux-gnu/sys/ucontext.h:36: note: this is the location of
the previous definition
# define REG_SP 2
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
disas/microblaze.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/disas/microblaze.c b/disas/microblaze.c
index 598ecbc89d..c23605043a 100644
--- a/disas/microblaze.c
+++ b/disas/microblaze.c
@@ -176,7 +176,6 @@ enum microblaze_instr_type {
#define REG_TLBSX 36869 /* MMU: TLB Search Index reg */
/* alternate names for gen purpose regs */
-#define REG_SP 1 /* stack pointer */
#define REG_ROSDP 2 /* read-only small data pointer */
#define REG_RWSDP 13 /* read-write small data pointer */
--
2.17.2
- [Qemu-devel] [PULL 13/42] tcg/riscv: Add the out load and store instructions, (continued)
- [Qemu-devel] [PULL 13/42] tcg/riscv: Add the out load and store instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 15/42] tcg/riscv: Add branch and jump instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 16/42] tcg/riscv: Add slowpath load and store instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 17/42] tcg/riscv: Add direct load and store instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 18/42] tcg/riscv: Add the out op decoder, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 19/42] tcg/riscv: Add the prologue generation and register the JIT, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 20/42] tcg/riscv: Add the target init code, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 21/42] tcg: Add RISC-V cpu signal handler, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 22/42] disas: Add RISC-V support, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 23/42] configure: Add support for building RISC-V host, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 24/42] disas/microblaze: Remove unused REG_SP macro,
Richard Henderson <=
- [Qemu-devel] [PULL 25/42] linux-user: Add safe_syscall for riscv64 host, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 26/42] tcg: Renumber TCG_CALL_* flags, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 27/42] tcg: Add TCG_CALL_NO_RETURN, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 28/42] tcg: Reference count labels, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 29/42] tcg: Add reachable_code_pass, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 30/42] tcg: Add preferred_reg argument to tcg_reg_alloc, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 31/42] tcg: Add preferred_reg argument to temp_load, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 32/42] tcg: Add preferred_reg argument to temp_sync, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 33/42] tcg: Add preferred_reg argument to tcg_reg_alloc_do_movi, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 34/42] tcg: Add output_pref to TCGOp, Richard Henderson, 2018/12/25