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[Qemu-devel] [PATCH 06/13] target: arm: Make ARM TLB filling routine sta
From: |
Samuel Ortiz |
Subject: |
[Qemu-devel] [PATCH 06/13] target: arm: Make ARM TLB filling routine static |
Date: |
Tue, 13 Nov 2018 17:52:40 +0100 |
It's only used in op_helper.c, it does not need to be exported and
moreover it should only be build when TCG is enabled.
Signed-off-by: Samuel Ortiz <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Robert Bradford <address@hidden>
---
target/arm/internals.h | 5 -----
target/arm/helper.c | 37 -------------------------------------
target/arm/op_helper.c | 38 ++++++++++++++++++++++++++++++++++++++
3 files changed, 38 insertions(+), 42 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index ffb5091b1f..06439467d2 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -741,11 +741,6 @@ static inline bool arm_extabort_type(MemTxResult result)
return result != MEMTX_DECODE_ERROR;
}
-/* Do a page table walk and add page to TLB if possible */
-bool arm_tlb_fill(CPUState *cpu, vaddr address,
- MMUAccessType access_type, int mmu_idx,
- ARMMMUFaultInfo *fi);
-
/* Return true if the stage 1 translation regime is using LPAE format page
* tables */
bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index bc2c8cdb67..689879c23a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8855,43 +8855,6 @@ bool get_phys_addr(CPUARMState *env, target_ulong
address,
}
}
-/* Walk the page table and (if the mapping exists) add the page
- * to the TLB. Return false on success, or true on failure. Populate
- * fsr with ARM DFSR/IFSR fault register format value on failure.
- */
-bool arm_tlb_fill(CPUState *cs, vaddr address,
- MMUAccessType access_type, int mmu_idx,
- ARMMMUFaultInfo *fi)
-{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
- hwaddr phys_addr;
- target_ulong page_size;
- int prot;
- int ret;
- MemTxAttrs attrs = {};
-
- ret = get_phys_addr(env, address, access_type,
- core_to_arm_mmu_idx(env, mmu_idx), &phys_addr,
- &attrs, &prot, &page_size, fi, NULL);
- if (!ret) {
- /*
- * Map a single [sub]page. Regions smaller than our declared
- * target page size are handled specially, so for those we
- * pass in the exact addresses.
- */
- if (page_size >= TARGET_PAGE_SIZE) {
- phys_addr &= TARGET_PAGE_MASK;
- address &= TARGET_PAGE_MASK;
- }
- tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
- prot, mmu_idx, page_size);
- return 0;
- }
-
- return ret;
-}
-
hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
MemTxAttrs *attrs)
{
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 44a74cb296..3b0459db50 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -179,6 +179,44 @@ static void deliver_fault(ARMCPU *cpu, vaddr addr,
MMUAccessType access_type,
raise_exception(env, exc, syn, target_el);
}
+/* Walk the page table and (if the mapping exists) add the page
+ * to the TLB. Return false on success, or true on failure. Populate
+ * fsr with ARM DFSR/IFSR fault register format value on failure.
+ */
+static bool arm_tlb_fill(CPUState *cs, vaddr address,
+ MMUAccessType access_type, int mmu_idx,
+ ARMMMUFaultInfo *fi)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ hwaddr phys_addr;
+ target_ulong page_size;
+ int prot;
+ int ret;
+ MemTxAttrs attrs = {};
+
+ ret = get_phys_addr(env, address, access_type,
+ core_to_arm_mmu_idx(env, mmu_idx), &phys_addr,
+ &attrs, &prot, &page_size, fi, NULL);
+ if (!ret) {
+ /*
+ * Map a single [sub]page. Regions smaller than our declared
+ * target page size are handled specially, so for those we
+ * pass in the exact addresses.
+ */
+ if (page_size >= TARGET_PAGE_SIZE) {
+ phys_addr &= TARGET_PAGE_MASK;
+ address &= TARGET_PAGE_MASK;
+ }
+ tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
+ prot, mmu_idx, page_size);
+ return 0;
+ }
+
+ return ret;
+}
+
+
/* try to fill the TLB and return an exception if error. If retaddr is
* NULL, it means that the function was called in C code (i.e. not
* from generated code or from helper.c)
--
2.19.1
- [Qemu-devel] [PATCH 08/13] target: arm: Move all VFP helpers into their own file, (continued)
- [Qemu-devel] [PATCH 08/13] target: arm: Move all VFP helpers into their own file, Samuel Ortiz, 2018/11/13
- [Qemu-devel] [PATCH 11/13] target: arm: Define TCG dependent functions when TCG is enabled, Samuel Ortiz, 2018/11/13
- [Qemu-devel] [PATCH 09/13] target: arm: Move CPU state dumping routines to helper.c, Samuel Ortiz, 2018/11/13
- [Qemu-devel] [PATCH 03/13] target: arm: Move all v7m helpers into their own file, Samuel Ortiz, 2018/11/13
- [Qemu-devel] [PATCH 05/13] target: arm: Move the DC ZVA helper into op_helper, Samuel Ortiz, 2018/11/13
- [Qemu-devel] [PATCH 07/13] target: arm: Remove the LDST headers, Samuel Ortiz, 2018/11/13
- [Qemu-devel] [PATCH 01/13] target: arm: Add copyright boilerplate, Samuel Ortiz, 2018/11/13
- [Qemu-devel] [PATCH 06/13] target: arm: Make ARM TLB filling routine static,
Samuel Ortiz <=
- [Qemu-devel] [PATCH 02/13] target: arm: Remove unused headers, Samuel Ortiz, 2018/11/13
Re: [Qemu-devel] [PATCH 00/13] Support disabling TCG on ARM, no-reply, 2018/11/14