[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 3/5] target/mips: Rename MMI-related functions
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 3/5] target/mips: Rename MMI-related functions |
Date: |
Tue, 30 Oct 2018 18:28:16 +0100 |
From: Aleksandar Markovic <address@hidden>
Rename MMI-related functions.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 42 +++++++++++++++++++++---------------------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 89126b4..dd96195 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -26337,7 +26337,7 @@ static void decode_opc_special3_legacy(CPUMIPSState
*env, DisasContext *ctx)
}
}
-static void decode_tx79_mmi0(CPUMIPSState *env, DisasContext *ctx)
+static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_MMI0(ctx->opcode);
@@ -26370,13 +26370,13 @@ static void decode_tx79_mmi0(CPUMIPSState *env,
DisasContext *ctx)
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI0 */
break;
default:
- MIPS_INVAL("TX79 MMI class MMI0");
+ MIPS_INVAL("MMI class MMI0");
generate_exception_end(ctx, EXCP_RI);
break;
}
}
-static void decode_tx79_mmi1(CPUMIPSState *env, DisasContext *ctx)
+static void decode_mmi1(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_MMI1(ctx->opcode);
@@ -26402,13 +26402,13 @@ static void decode_tx79_mmi1(CPUMIPSState *env,
DisasContext *ctx)
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI1 */
break;
default:
- MIPS_INVAL("TX79 MMI class MMI1");
+ MIPS_INVAL("MMI class MMI1");
generate_exception_end(ctx, EXCP_RI);
break;
}
}
-static void decode_tx79_mmi2(CPUMIPSState *env, DisasContext *ctx)
+static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_MMI2(ctx->opcode);
@@ -26438,13 +26438,13 @@ static void decode_tx79_mmi2(CPUMIPSState *env,
DisasContext *ctx)
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI2 */
break;
default:
- MIPS_INVAL("TX79 MMI class MMI2");
+ MIPS_INVAL("MMI class MMI2");
generate_exception_end(ctx, EXCP_RI);
break;
}
}
-static void decode_tx79_mmi3(CPUMIPSState *env, DisasContext *ctx)
+static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_MMI3(ctx->opcode);
@@ -26465,13 +26465,13 @@ static void decode_tx79_mmi3(CPUMIPSState *env,
DisasContext *ctx)
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
break;
default:
- MIPS_INVAL("TX79 MMI class MMI3");
+ MIPS_INVAL("MMI class MMI3");
generate_exception_end(ctx, EXCP_RI);
break;
}
}
-static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
+static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_MMI(ctx->opcode);
int rs = extract32(ctx->opcode, 21, 5);
@@ -26480,16 +26480,16 @@ static void decode_tx79_mmi(CPUMIPSState *env,
DisasContext *ctx)
switch (opc) {
case MMI_OPC_CLASS_MMI0:
- decode_tx79_mmi0(env, ctx);
+ decode_mmi0(env, ctx);
break;
case MMI_OPC_CLASS_MMI1:
- decode_tx79_mmi1(env, ctx);
+ decode_mmi1(env, ctx);
break;
case MMI_OPC_CLASS_MMI2:
- decode_tx79_mmi2(env, ctx);
+ decode_mmi2(env, ctx);
break;
case MMI_OPC_CLASS_MMI3:
- decode_tx79_mmi3(env, ctx);
+ decode_mmi3(env, ctx);
break;
case MMI_OPC_MULT1:
case MMI_OPC_MULTU1:
@@ -26523,18 +26523,18 @@ static void decode_tx79_mmi(CPUMIPSState *env,
DisasContext *ctx)
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_CLASS_MMI */
break;
default:
- MIPS_INVAL("TX79 MMI class");
+ MIPS_INVAL("MMI class");
generate_exception_end(ctx, EXCP_RI);
break;
}
}
-static void decode_tx79_lq(CPUMIPSState *env, DisasContext *ctx)
+static void decode_mmi_lq(CPUMIPSState *env, DisasContext *ctx)
{
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_LQ */
}
-static void gen_tx79_sq(DisasContext *ctx, int base, int rt, int offset)
+static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
{
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_SQ */
}
@@ -26560,7 +26560,7 @@ static void gen_tx79_sq(DisasContext *ctx, int base,
int rt, int offset)
* In user mode, QEMU must verify the upper and lower 11 bits to distinguish
* between SQ and RDHWR, as the Linux kernel does.
*/
-static void decode_tx79_sq(CPUMIPSState *env, DisasContext *ctx)
+static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx)
{
int base = extract32(ctx->opcode, 21, 5);
int rt = extract32(ctx->opcode, 16, 5);
@@ -26578,7 +26578,7 @@ static void decode_tx79_sq(CPUMIPSState *env,
DisasContext *ctx)
}
#endif
- gen_tx79_sq(ctx, base, rt, offset);
+ gen_mmi_sq(ctx, base, rt, offset);
}
static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
@@ -27887,7 +27887,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
case OPC_SPECIAL2:
if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
- decode_tx79_mmi(env, ctx);
+ decode_mmi(env, ctx);
} else if (ctx->insn_flags & ASE_MXU) {
decode_opc_mxu(env, ctx);
} else {
@@ -27896,7 +27896,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
case OPC_SPECIAL3:
if (ctx->insn_flags & INSN_R5900) {
- decode_tx79_sq(env, ctx); /* MMI_SQ */
+ decode_mmi_sq(env, ctx); /* MMI_SQ */
} else {
decode_opc_special3(env, ctx);
}
@@ -28560,7 +28560,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
case OPC_MSA: /* OPC_MDMX */
if (ctx->insn_flags & INSN_R5900) {
- decode_tx79_lq(env, ctx); /* MMI_LQ */
+ decode_mmi_lq(env, ctx); /* MMI_LQ */
} else {
/* MDMX: Not implemented. */
gen_msa(env, ctx);
--
2.7.4
- [Qemu-devel] [PULL 0/5] MIPS queue for October 2018, part 5, Aleksandar Markovic, 2018/10/30
- [Qemu-devel] [PULL 5/5] target/mips: Enable only tested modes for R5900, Aleksandar Markovic, 2018/10/30
- [Qemu-devel] [PULL 1/5] target/mips: Rename MMI-related masks, Aleksandar Markovic, 2018/10/30
- [Qemu-devel] [PULL 2/5] target/mips: Rename MMI-related opcodes, Aleksandar Markovic, 2018/10/30
- [Qemu-devel] [PULL 4/5] target/mips: Remove some spurious R5900-related comments, Aleksandar Markovic, 2018/10/30
- [Qemu-devel] [PULL 3/5] target/mips: Rename MMI-related functions,
Aleksandar Markovic <=
- Re: [Qemu-devel] [PULL 0/5] MIPS queue for October 2018, part 5, Philippe Mathieu-Daudé, 2018/10/30