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Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R
From: |
Fredrik Noring |
Subject: |
Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 |
Date: |
Thu, 25 Oct 2018 19:01:28 +0200 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
Hi Richard,
> > Option 3: Extend the mips_opcode::membership field.
>
> It's trivial to extend the field to uint64_t.
Is the membership field intended to be used? The opcodes for CLZ and CLO
clash with the R5900 opcodes for MADD1 and MADDU1, resulting in incorrect
disassembly of MADD1 and MADDU1. For example:
0x70853020 madd1 a2,a0,a1 disassembles into clz a2 or a1,a0
0x70853021 maddu1 a2,a0,a1 disassembles into clo a2 or a1,a0
(CLZ and CLO are members of I32|N55, whereas MADD1 and MADDU1 are EE.)
Fredrik
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -2549,12 +2553,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,
0, G1 },
{"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0,
D33 },
{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M,
0, G1 },
+{"madd1", "s,t", 0x70000020, 0xfc00ffff, RD_s | RD_t | WR_HILO | IS_M, 0, EE },
+{"madd1", "d,s,t", 0x70000020, 0xfc0007ff, RD_s | RD_t | WR_HILO | WR_d |
IS_M, 0, EE },
{"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO,
0, SMT },
{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,
0, L1 },
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,
0, I32|N55 },
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,
0, G1 },
{"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0,
D33 },
{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M,
0, G1 },
+{"maddu1", "s,t", 0x70000021, 0xfc00ffff, RD_s | RD_t | WR_HILO | IS_M, 0, EE
},
+{"maddu1", "d,s,t", 0x70000021, 0xfc0007ff, RD_s | RD_t | WR_HILO | WR_d |
IS_M, 0, EE },
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0,
N411 },
{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0,
MX|SB1 },
{"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0,
N54 },
- [Qemu-devel] [PULL 25/34] tests/tcg/mips: Test R5900 three-operand MULT1, (continued)
- [Qemu-devel] [PULL 25/34] tests/tcg/mips: Test R5900 three-operand MULT1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 29/34] tests/tcg/mips: Test R5900 DIV1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 31/34] target/mips: Define the R5900 CPU, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 27/34] tests/tcg/mips: Test R5900 MFLO1 and MFHI1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 32/34] linux-user/mips: Recognise the R5900 CPU model, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 33/34] target/mips: Fix the title of translate.c, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 34/34] target/mips: Fix decoding of ALIGN and DALIGN instructions, Aleksandar Markovic, 2018/10/22
- Re: [Qemu-devel] [PULL 00/34] MIPS queue for October 2018 - part 2, Peter Maydell, 2018/10/23
- Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900, Fredrik Noring, 2018/10/23
- Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900, Richard Henderson, 2018/10/24
- Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900,
Fredrik Noring <=
- Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900, Maciej W. Rozycki, 2018/10/25
- Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900, Fredrik Noring, 2018/10/25
- Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900, Richard Henderson, 2018/10/26
- Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900, Maciej W. Rozycki, 2018/10/26