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Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R
From: |
Fredrik Noring |
Subject: |
Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 |
Date: |
Thu, 25 Oct 2018 20:20:46 +0200 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
Hi Maciej,
> > Is the membership field intended to be used? The opcodes for CLZ and CLO
> > clash with the R5900 opcodes for MADD1 and MADDU1, resulting in incorrect
> > disassembly of MADD1 and MADDU1. For example:
> >
> > 0x70853020 madd1 a2,a0,a1 disassembles into clz a2 or a1,a0
> > 0x70853021 maddu1 a2,a0,a1 disassembles into clo a2 or a1,a0
> >
> > (CLZ and CLO are members of I32|N55, whereas MADD1 and MADDU1 are EE.)
>
> It looks like a disassembler bug somewhere then (maybe in your patched
> version only), because the R5900 is not supposed to match I32 (because it
> does not implement the MIPS32 ISA; it's only MIPS I aka I1 with additions
> or MIPS IV aka I4 with exclusions, or anything between with both additions
> and exclusions, with I believe MIPS III aka I3 being the closest match),
> and it is not supposed to match N55 either (because it is obviously not a
> Vr5500 processor).
I think the "bug" is that the membership field is defined but unused, so
opcode memberships are simply ignored. OPCODE_IS_MEMBER is defined to be
always true, for all opcodes and all ISAs.
> Overall this source file is clearly a modified copy of an ancient version
> of the opcode table included with the opcodes library from binutils and I
> think it would benefit from a refresh. In particular separating an ASE
> field and adding an exclusions field, as it has been done with opcodes,
> would make it much easier to maintain this table. The table in opcodes is
> already messy due to several exceptions to the alphabetical order (and it
> could be improved a bit I believe), but I find its QEMU version even
> messier.
Agreed! QEMU's scripts/checkpatch.pl warns and errors on 80 and 90 column
violations, so trying avoid check breakage leaves the table unaligned too.
Fredrik
- [Qemu-devel] [PULL 31/34] target/mips: Define the R5900 CPU, (continued)
- [Qemu-devel] [PULL 31/34] target/mips: Define the R5900 CPU, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 27/34] tests/tcg/mips: Test R5900 MFLO1 and MFHI1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 32/34] linux-user/mips: Recognise the R5900 CPU model, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 33/34] target/mips: Fix the title of translate.c, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 34/34] target/mips: Fix decoding of ALIGN and DALIGN instructions, Aleksandar Markovic, 2018/10/22
- Re: [Qemu-devel] [PULL 00/34] MIPS queue for October 2018 - part 2, Peter Maydell, 2018/10/23
- Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900, Fredrik Noring, 2018/10/23
- Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900, Richard Henderson, 2018/10/24
- Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900, Fredrik Noring, 2018/10/25
- Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900, Maciej W. Rozycki, 2018/10/25
- Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900,
Fredrik Noring <=
- Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900, Richard Henderson, 2018/10/26
- Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900, Maciej W. Rozycki, 2018/10/26