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Re: [Qemu-devel] [PATCH v5 22/28] target/mips: Add CP0 Config2 to DisasC
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH v5 22/28] target/mips: Add CP0 Config2 to DisasContext |
Date: |
Mon, 15 Oct 2018 00:22:59 +0200 |
On Fri, Oct 12, 2018 at 6:58 PM Aleksandar Markovic
<address@hidden> wrote:
>
> From: Stefan Markovic <address@hidden>
>
> Add field corresponding to CP0 Config2 to DisasContext. This is
> needed for availability control via Config2 bits.
>
> Signed-off-by: Stefan Markovic <address@hidden>
> Signed-off-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> target/mips/translate.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index e7bc3d4..9e4aae5 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1449,6 +1449,7 @@ typedef struct DisasContext {
> uint32_t opcode;
> int insn_flags;
> int32_t CP0_Config1;
> + int32_t CP0_Config2;
> int32_t CP0_Config3;
> int32_t CP0_Config5;
> /* Routine used to access memory */
> @@ -25517,6 +25518,7 @@ static void
> mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->saved_pc = -1;
> ctx->insn_flags = env->insn_flags;
> ctx->CP0_Config1 = env->CP0_Config1;
> + ctx->CP0_Config2 = env->CP0_Config2;
> ctx->CP0_Config3 = env->CP0_Config3;
> ctx->CP0_Config5 = env->CP0_Config5;
> ctx->btarget = 0;
> --
> 2.7.4
>
>
- [Qemu-devel] [PATCH v5 17/28] target/mips: Add bit definitions for DSP R3 ASE, (continued)
- [Qemu-devel] [PATCH v5 17/28] target/mips: Add bit definitions for DSP R3 ASE, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 20/28] target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 16/28] target/mips: Add CP0 SAARI and SAAR registers, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 15/28] target/mips: Add CPO MemoryMapID register, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 18/28] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 14/28] target/mips: Extend WatchHi registers, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 22/28] target/mips: Add CP0 Config2 to DisasContext, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 26/28] target/mips: Add DEC feature to mips32r6-generic CPU, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 23/28] target/mips: Implement emulation of nanoMIPS EVA instructions, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 27/28] target/mips: Add MSA ASE to MIPS64R2-generic CPU, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 25/28] hw/mips: Add Data Scratch Pad RAM, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 21/28] target/mips: Add opcodes for nanoMIPS EVA instructions, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 24/28] hw/mips: Update ITU to utilise SAARI/SAAR registers, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 28/28] target/mips: Add I6500 core configuration, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 19/28] target/mips: Improve DSP R2/R3-related naming, Aleksandar Markovic, 2018/10/12