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[Qemu-devel] [PATCH v5 20/28] target/mips: Fix emulation of microMIPS R6
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v5 20/28] target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S> |
Date: |
Fri, 12 Oct 2018 18:39:28 +0200 |
From: Matthew Fortune <address@hidden>
Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S> instructions.
Their handling was permuted.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Matthew Fortune <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1d31051..f76dfda 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -15197,15 +15197,15 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
case 0x38:
/* cmovs */
switch ((ctx->opcode >> 6) & 0x7) {
- case MOVN_FMT: /* SELNEZ_FMT */
+ case MOVN_FMT: /* SELEQZ_FMT */
if (ctx->insn_flags & ISA_MIPS32R6) {
- /* SELNEZ_FMT */
+ /* SELEQZ_FMT */
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
- gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
+ gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
break;
case FMT_SDPS_D:
- gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
+ gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
break;
default:
goto pool32f_invalid;
@@ -15219,15 +15219,15 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
check_insn_opc_removed(ctx, ISA_MIPS32R6);
FINSN_3ARG_SDPS(MOVN);
break;
- case MOVZ_FMT: /* SELEQZ_FMT */
+ case MOVZ_FMT: /* SELNEZ_FMT */
if (ctx->insn_flags & ISA_MIPS32R6) {
- /* SELEQZ_FMT */
+ /* SELNEZ_FMT */
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
- gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
+ gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
break;
case FMT_SDPS_D:
- gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
+ gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
break;
default:
goto pool32f_invalid;
--
2.7.4
- [Qemu-devel] [PATCH v5 06/28] linux-user: Add fields that correspond to kernel arch_elf_state, (continued)
- [Qemu-devel] [PATCH v5 06/28] linux-user: Add fields that correspond to kernel arch_elf_state, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 07/28] linux-user: Add the field for kernel thread info flags, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 08/28] target/mips: Add CPO PWBase register, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 09/28] target/mips: Add CPO PWField register, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 10/28] target/mips: Add CPO PWSize register, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 11/28] target/mips: Add CPO PWCtl register, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 12/28] target/mips: Add reset state for PWSize and PWField registers, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 13/28] target/mips: Implement hardware page table walker, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 17/28] target/mips: Add bit definitions for DSP R3 ASE, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 20/28] target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v5 16/28] target/mips: Add CP0 SAARI and SAAR registers, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 15/28] target/mips: Add CPO MemoryMapID register, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 18/28] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 14/28] target/mips: Extend WatchHi registers, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 22/28] target/mips: Add CP0 Config2 to DisasContext, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 26/28] target/mips: Add DEC feature to mips32r6-generic CPU, Aleksandar Markovic, 2018/10/12