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[Qemu-devel] [PATCH v4 03/22] elf: Add Mips_elf_abiflags_v0 structure
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v4 03/22] elf: Add Mips_elf_abiflags_v0 structure |
Date: |
Thu, 11 Oct 2018 13:22:08 +0200 |
From: Stefan Markovic <address@hidden>
Add Mips_elf_abiflags_v0 structure to elf.h. The source of information
is kernel header arch/mips/include/asm/elf.h.
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
include/elf.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index eb5958d..75c60cc 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -96,6 +96,21 @@ typedef int64_t Elf64_Sxword;
#define MIPS_ABI_FP_64 0x6 /* -mips32r2 -mfp64 */
#define MIPS_ABI_FP_64A 0x7 /* -mips32r2 -mfp64 -mno-odd-spreg */
+typedef struct mips_elf_abiflags_v0 {
+ uint16_t version; /* Version of flags structure */
+ uint8_t isa_level; /* The level of the ISA: 1-5, 32, 64 */
+ uint8_t isa_rev; /* The revision of ISA: 0 for MIPS V and below,*/
+ /* 1-n otherwise */
+ uint8_t gpr_size; /* The size of general purpose registers */
+ uint8_t cpr1_size; /* The size of co-processor 1 registers */
+ uint8_t cpr2_size; /* The size of co-processor 2 registers */
+ uint8_t fp_abi; /* The floating-point ABI */
+ uint32_t isa_ext; /* Mask of processor-specific extensions */
+ uint32_t ases; /* Mask of ASEs used */
+ uint32_t flags1; /* Mask of general flags */
+ uint32_t flags2;
+} Mips_elf_abiflags_v0;
+
/* These constants define the different elf file types */
#define ET_NONE 0
#define ET_REL 1
--
2.7.4
- [Qemu-devel] [PATCH v4 05/22] target/mips: Add CPO PWField register, (continued)
- [Qemu-devel] [PATCH v4 05/22] target/mips: Add CPO PWField register, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 06/22] target/mips: Add CPO PWSize register, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 02/22] elf: Add MIPS_ABI_FP_XXX constants, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 07/22] target/mips: Add CPO PWCtl register, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 08/22] target/mips: Implement hardware page table walker, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 03/22] elf: Add Mips_elf_abiflags_v0 structure,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v4 09/22] target/mips: Extend WatchHi registers, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 10/22] target/mips: Add CPO MemoryMapID register, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 04/22] target/mips: Add CPO PWBase register, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 11/22] target/mips: Add CP0 SAARI and SAAR registers, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 12/22] target/mips: Add bit definitions for DSP R3 ASE, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 13/22] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 14/22] target/mips: Improve DSP R2/R3-related naming, Aleksandar Markovic, 2018/10/11