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[Qemu-devel] [PATCH v4 07/22] target/mips: Add CPO PWCtl register
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v4 07/22] target/mips: Add CPO PWCtl register |
Date: |
Thu, 11 Oct 2018 13:22:12 +0200 |
From: Yongbok Kim <address@hidden>
Add PWCtl register (CP0 Register 5, Select 6).
The PWCtl register configures hardware page table walking for TLB
refills.
This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:
PWEn (31) - Hardware Page Table walker enable
DPH (7) - Dual Page format of Huge Page support
HugePg (6) - Huge Page PTE supported in Directory levels
PSn (5..0) - Bit position of PTEvld in Huge Page PTE
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/cpu.h | 5 +++++
target/mips/helper.h | 1 +
target/mips/machine.c | 1 +
target/mips/op_helper.c | 10 ++++++++++
target/mips/translate.c | 20 ++++++++++++++++++++
5 files changed, 37 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index a6abd1f..5e45e97 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -304,6 +304,11 @@ struct CPUMIPSState {
#define CP0PS_PTW 6 /* 11..6 */
#define CP0PS_PTEW 0 /* 5..0 */
int32_t CP0_Wired;
+ int32_t CP0_PWCtl;
+#define CP0PC_PWEN 31
+#define CP0PC_DPH 7
+#define CP0PC_HUGEPG 6
+#define CP0PC_PSN 0 /* 5..0 */
int32_t CP0_SRSConf0_rw_bitmask;
int32_t CP0_SRSConf0;
#define CP0SRSC0_M 31
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 169890a..c23e4e5 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -129,6 +129,7 @@ DEF_HELPER_2(mtc0_srsconf2, void, env, tl)
DEF_HELPER_2(mtc0_srsconf3, void, env, tl)
DEF_HELPER_2(mtc0_srsconf4, void, env, tl)
DEF_HELPER_2(mtc0_hwrena, void, env, tl)
+DEF_HELPER_2(mtc0_pwctl, void, env, tl)
DEF_HELPER_2(mtc0_count, void, env, tl)
DEF_HELPER_2(mtc0_entryhi, void, env, tl)
DEF_HELPER_2(mttc0_entryhi, void, env, tl)
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 31e3d95..67a85a0 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -260,6 +260,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU),
VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU),
VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
+ VMSTATE_INT32(env.CP0_PWCtl, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 0986baf..e649bd0 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1524,6 +1524,16 @@ void helper_mtc0_srsconf4(CPUMIPSState *env,
target_ulong arg1)
env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
}
+void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1)
+{
+#ifdef TARGET_MIPS64
+ /* PWEn = 0. Hardware page table walking is not implemented. */
+ env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F);
+#else
+ env->CP0_PWCtl = (arg1 & 0x800000FF);
+#endif
+}
+
void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
{
uint32_t mask = 0x0000000F;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ef38be9..f669d48 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5598,6 +5598,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
rn = "SRSConf4";
break;
+ case 6:
+ check_pw(ctx);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
+ rn = "PWCtl";
+ break;
default:
goto cp0_unimplemented;
}
@@ -6314,6 +6319,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
gen_helper_mtc0_srsconf4(cpu_env, arg);
rn = "SRSConf4";
break;
+ case 6:
+ check_pw(ctx);
+ gen_helper_mtc0_pwctl(cpu_env, arg);
+ rn = "PWCtl";
+ break;
default:
goto cp0_unimplemented;
}
@@ -7039,6 +7049,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
rn = "SRSConf4";
break;
+ case 6:
+ check_pw(ctx);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
+ rn = "PWCtl";
+ break;
default:
goto cp0_unimplemented;
}
@@ -7737,6 +7752,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
gen_helper_mtc0_srsconf4(cpu_env, arg);
rn = "SRSConf4";
break;
+ case 6:
+ check_pw(ctx);
+ gen_helper_mtc0_pwctl(cpu_env, arg);
+ rn = "PWCtl";
+ break;
default:
goto cp0_unimplemented;
}
--
2.7.4
- [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 01/22] elf: Fix PT_MIPS_XXX constants, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 05/22] target/mips: Add CPO PWField register, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 06/22] target/mips: Add CPO PWSize register, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 02/22] elf: Add MIPS_ABI_FP_XXX constants, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 07/22] target/mips: Add CPO PWCtl register,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v4 08/22] target/mips: Implement hardware page table walker, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 03/22] elf: Add Mips_elf_abiflags_v0 structure, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 09/22] target/mips: Extend WatchHi registers, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 10/22] target/mips: Add CPO MemoryMapID register, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 04/22] target/mips: Add CPO PWBase register, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 11/22] target/mips: Add CP0 SAARI and SAAR registers, Aleksandar Markovic, 2018/10/11