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Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific thre
From: |
Maciej W. Rozycki |
Subject: |
Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU |
Date: |
Fri, 28 Sep 2018 16:59:46 +0100 (BST) |
User-agent: |
Alpine 2.21 (LFD 202 2017-01-01) |
On Fri, 28 Sep 2018, Philippe Mathieu-Daudé wrote:
> > > Note, these instructions are also valid on the R3900 (which also has
> > > MADD/MADDU).
> > >
> > > Would gen_mul_toshiba() be a better common name? I don't like it but
> > > can't think of another.
> >
> > I propose gen_mul_3op, since its distinctive feature is the three operands.
>
> Fine by me.
Bikeshedding, but... I haven't looked at how we implement it, however
generic MIPS architecture also has a 3-operand MUL instruction defined,
reusing, for R1-R5, the encoding used earlier on by IDT R4650 and NEC
Vr5500, and using a different one for R6. So I'd rather we avoided
confusion here.
Perhaps `gen_mul_ee' then for Emotion Engine? -- EE is what libopcodes
uses for R5900 instructions where brevity matters. Or `gen_mul_4op',
because we have 4 operands really, with the HI/LO accumulator being an
implicit one.
What's wrong with `gen_mul_r5900' anyway?
Maciej
- [Qemu-devel] [PATCH v5 1/8] target/mips: Define R5900 instructions and CPU preprocessor constants, (continued)
- [Qemu-devel] [PATCH v5 1/8] target/mips: Define R5900 instructions and CPU preprocessor constants, Fredrik Noring, 2018/09/19
- [Qemu-devel] [PATCH v5 4/8] target/mips: Add function to signal RI exception unless user only, Fredrik Noring, 2018/09/19
- [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, Fredrik Noring, 2018/09/19
- Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, Philippe Mathieu-Daudé, 2018/09/26
- Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, Maciej W. Rozycki, 2018/09/26
- Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, Fredrik Noring, 2018/09/28
- Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, Philippe Mathieu-Daudé, 2018/09/28
- Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU,
Maciej W. Rozycki <=
- Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, Philippe Mathieu-Daudé, 2018/09/28
- Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, Maciej W. Rozycki, 2018/09/28
[Qemu-devel] [PATCH v5 3/8] target/mips: Support R5900 instructions MOVN, MOVZ and PREF from MIPS IV, Fredrik Noring, 2018/09/19
[Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Fredrik Noring, 2018/09/19
- Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Philippe Mathieu-Daudé, 2018/09/20
- Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Philippe Mathieu-Daudé, 2018/09/20
- Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Maciej W. Rozycki, 2018/09/20
- Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Philippe Mathieu-Daudé, 2018/09/24
- Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Maciej W. Rozycki, 2018/09/25
- Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Philippe Mathieu-Daudé, 2018/09/25