Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU

[Philippe Mathieu-Daudé]

On Fri, Sep 28, 2018 at 5:59 PM Maciej W. Rozycki <address@hidden> wrote:
>
> On Fri, 28 Sep 2018, Philippe Mathieu-Daudé wrote:
>
> > > > Note, these instructions are also valid on the R3900 (which also has
> > > > MADD/MADDU).
> > > >
> > > > Would gen_mul_toshiba() be a better common name? I don't like it but
> > > > can't think of another.
> > >
> > > I propose gen_mul_3op, since its distinctive feature is the three 
> > > operands.
> >
> > Fine by me.
>
>  Bikeshedding, but...  I haven't looked at how we implement it, however
> generic MIPS architecture also has a 3-operand MUL instruction defined,
> reusing, for R1-R5, the encoding used earlier on by IDT R4650 and NEC
> Vr5500, and using a different one for R6.  So I'd rather we avoided
> confusion here.
>
>  Perhaps `gen_mul_ee' then for Emotion Engine? -- EE is what libopcodes
> uses for R5900 instructions where brevity matters.  Or `gen_mul_4op',
> because we have 4 operands really, with the HI/LO accumulator being an
> implicit one.
>
>  What's wrong with `gen_mul_r5900' anyway?

I plan to use this function (adding MADD/MADDU) for R3900 based cores
(which don't seemt related to Emotion Engine).