Re: [Qemu-devel] [PATCH 6/6] x86_iommu/amd: Enable Guest virtual APIC support

[Brijesh Singh]

On 09/11/2018 11:52 PM, Peter Xu wrote:
...

> > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > index 5c2c638..1cbc8ba 100644
> > --- a/hw/i386/acpi-build.c
> > +++ b/hw/i386/acpi-build.c
> > @@ -2565,7 +2565,8 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linker)
> >       build_append_int_noprefix(table_data,
> >                                (48UL << 30) | /* HATS   */
> >                                (48UL << 28) | /* GATS   */
> > -                             (1UL << 2),    /* GTSup  */
> > +                             (1UL << 2)   | /* GTSup  */
> > +                             (1UL << 6),    /* GASup  */
>
> Sorry if I misunderstood - is this for nested?
>
> I'm a bit confused here... IIUC in your previous patches you didn't
> really implement guest_mode==1 case in IRTEs.  So if you have this set
> then the guest should be able to setup IRTEs with guest_mode==1?  How
> did it work?

Yes, sometime spec can be confusing ;) let me see if I can explain it.

Suravee, please correct me if I misunderstood something

- A legacy interrupt remap support is available on all IOMMU versions.

  Guest OS makes the decision whether to use the feature. Guest OS
  sets the IV bit in DTE to indicate when there is a valid interrupt
  map (See Table 7 DTE definition).

  In this mode, IRTE is 32-bit. The field details are available
  in Table 20 - Section 2.2.5.2. The third patch in this series
  implements the support for this case.

  (NOTE: As I explained [1], the Linux guest enables intr remap only
   when it sees a special IVHD IOAPIC type device is present in IVRS)

  [1] https://marc.info/?l=qemu-devel&m=153677956506196&w=2

- When AVIC is used in the guest, the intr remap logic is different.

  Based on the guest_mode, IOMMU and AVIC may need to work together
  to remap the interrupts (IOMMU spec refers this as Guest Virtual APIC
  Enabled -- Section 2.2.5.3).

  The GASup bit in extended feature register and IVHD IOMMU feature
  reporting field in IVRS are used to tell whether the IOMMU supports
  intr remap when AVIC is enabled in the guest.

  In this mode, the IRTE is 128-bit.

  To make things interesting, there is a GAMSup bit in extended
  feature register. It is used by IOMMU to tell the AVIC supported
  modes:

  a) 0 = intr_remap only (i.e IOMMU can remap the interrupt on its own)
  b) 1 = Both guest AVIC and IOMMU will work together to remap the intr

  The patch 5 in the series implements the intr_remap (#a)

  I have not implemented the mode=1. I am not sure if its worth
  implementing this mode for the emulated IOMMU case.

  See Table 21 for control knobs from IOMMU. This patch series
  implements the first three rows.

I hope my explanation does not add more confusions ;)

-Brijesh