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[Qemu-devel] [PULL 18/52] hw/arm/boot: AArch32 kernels should be started
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 18/52] hw/arm/boot: AArch32 kernels should be started in Hyp mode if available |
Date: |
Fri, 24 Aug 2018 10:33:09 +0100 |
The kernel booting specification for an AArch32 kernel requires that
it is booted in Hyp mode if available; otherwise the kernel can't
enable KVM. We were incorrectly leaving the kernel in SVC mode.
If we're booting an AArch32 kernel in the Nonsecure state and Hyp
mode is available, start in it.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
---
hw/arm/boot.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index ca9467e583f..20c71d7d961 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -736,6 +736,17 @@ static void do_cpu_reset(void *opaque)
}
}
+ if (!env->aarch64 && !info->secure_boot &&
+ arm_feature(env, ARM_FEATURE_EL2)) {
+ /*
+ * This is an AArch32 boot not to Secure state, and
+ * we have Hyp mode available, so boot the kernel into
+ * Hyp mode. This is not how the CPU comes out of reset,
+ * so we need to manually put it there.
+ */
+ cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw);
+ }
+
if (cs == first_cpu) {
AddressSpace *as = arm_boot_address_space(cpu, info);
--
2.18.0
- [Qemu-devel] [PULL 03/52] target/arm: Use the int-to-float-scale softfloat routines, (continued)
- [Qemu-devel] [PULL 03/52] target/arm: Use the int-to-float-scale softfloat routines, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 01/52] softfloat: Add scaling int-to-float routines, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 08/52] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 11/52] hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 09/52] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 12/52] hw/arm/vexpress: Add "virtualization" property controlling presence of EL2, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 13/52] target/arm: Implement RAZ/WI HACTLR2, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 15/52] target/arm: Factor out code for taking an AArch32 exception, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 10/52] hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 16/52] target/arm: Implement support for taking exceptions to Hyp mode, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 18/52] hw/arm/boot: AArch32 kernels should be started in Hyp mode if available,
Peter Maydell <=
- [Qemu-devel] [PULL 19/52] hw/misc/mps2-fpgaio: Implement 1Hz and 100Hz counters, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 14/52] target/arm: Implement AArch32 HCR and HCR2, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 17/52] target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 20/52] hw/misc/mps2-fpgaio: Implement PSCNTR and COUNTER, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 21/52] hw/timer/cmsdk-apb-dualtimer: Implement CMSDK dual timer module, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 22/52] hw/arm/iotkit: Wire up the dualtimer, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 23/52] hw/arm/mps2: Wire up dual-timer in mps2-an385 and mps2-an511, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 24/52] hw/arm/iotkit: Wire up the watchdogs, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 25/52] hw/arm/iotkit: Wire up the S32KTIMER, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 26/52] hw/misc/iotkit-sysctl: Implement IoTKit system control element, Peter Maydell, 2018/08/24