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[Qemu-devel] [PULL 09/52] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 09/52] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ |
Date: |
Fri, 24 Aug 2018 10:33:00 +0100 |
Connect the VIRQ and VFIQ lines from the GIC to the CPU;
these exist always for both CPU and GIC whether the
virtualization extensions are enabled or not, so we
can just unconditionally connect them.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
---
hw/arm/fsl-imx7.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index d5e26855a55..7663ad68610 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -209,6 +209,10 @@ static void fsl_imx7_realize(DeviceState *dev, Error
**errp)
sysbus_connect_irq(sbd, i, irq);
irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
sysbus_connect_irq(sbd, i + smp_cpus, irq);
+ irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
+ sysbus_connect_irq(sbd, i + 2 * smp_cpus, irq);
+ irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
+ sysbus_connect_irq(sbd, i + 3 * smp_cpus, irq);
}
/*
--
2.18.0
- [Qemu-devel] [PULL 00/52] target-arm queue, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 04/52] target/arm: Use the float-to-int-scale softfloat routines, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 07/52] hw/arm/highbank: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 02/52] softfloat: Add scaling float-to-int routines, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 06/52] hw/arm/vexpress: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 05/52] hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes large, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 03/52] target/arm: Use the int-to-float-scale softfloat routines, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 01/52] softfloat: Add scaling int-to-float routines, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 08/52] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 11/52] hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 09/52] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ,
Peter Maydell <=
- [Qemu-devel] [PULL 12/52] hw/arm/vexpress: Add "virtualization" property controlling presence of EL2, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 13/52] target/arm: Implement RAZ/WI HACTLR2, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 15/52] target/arm: Factor out code for taking an AArch32 exception, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 10/52] hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 16/52] target/arm: Implement support for taking exceptions to Hyp mode, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 18/52] hw/arm/boot: AArch32 kernels should be started in Hyp mode if available, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 19/52] hw/misc/mps2-fpgaio: Implement 1Hz and 100Hz counters, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 14/52] target/arm: Implement AArch32 HCR and HCR2, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 17/52] target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 20/52] hw/misc/mps2-fpgaio: Implement PSCNTR and COUNTER, Peter Maydell, 2018/08/24