Re: [Qemu-devel] [PATCH v3 13/40] target/mips: Add emulation of misc nanoMIPS instructions (pool32a0)

[Richard Henderson]

On 07/19/2018 05:54 AM, Stefan Markovic wrote:
> From: Yongbok Kim <address@hidden>
> 
> Add emulation of nanoMIPS instructions that are situated in pool32a0.
> 
> Signed-off-by: Yongbok Kim <address@hidden>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> Signed-off-by: Stefan Markovic <address@hidden>
> Reviewed-by: Aleksandar Markovic <address@hidden>
> ---
>  target/mips/translate.c | 190 
> ++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 190 insertions(+)
> 
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 2c7f62e..81c2950 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -16588,6 +16588,186 @@ static void gen_pool16c_nanomips_insn(DisasContext 
> *ctx)
>      }
>  }
>  
> +static void gen_pool32a0_nanomips_insn(DisasContext *ctx)
> +{
> +    int rt = (ctx->opcode >> 21) & 0x1f;
> +    int rs = (ctx->opcode >> 16) & 0x1f;
> +    int rd = (ctx->opcode >> 11) & 0x1f;

extract32.

> +    case NM_SOV:
> +    {
> +        TCGv t0 = tcg_temp_local_new();
> +        TCGv t1 = tcg_temp_new();
> +        TCGv t2 = tcg_temp_new();
> +        TCGLabel *l1 = gen_new_label();
> +
> +        gen_load_gpr(t1, rs);
> +        gen_load_gpr(t2, rt);
> +        tcg_gen_add_tl(t0, t1, t2);
> +        tcg_gen_ext32s_tl(t0, t0);
> +        tcg_gen_xor_tl(t1, t1, t2);
> +        tcg_gen_xor_tl(t2, t0, t2);
> +        tcg_gen_andc_tl(t1, t2, t1);
> +
> +        tcg_gen_movi_tl(t0, 0);
> +        tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);

tcg_gen_setcondi_tl.


r~